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1 confidential eapp hybrid digital 4-phase green pwm controller for digital power management of core and memory with auto phase shedding ISL6381 the ISL6381 is an eapp hybrid digital 4-phase pwm controller and is designed to be comp liant to intel vr12.5/vr12 specifications and control the microprocessor core or memory voltage regulator. it includes programmable functions and telemetries for easy use, high system flexibility and overclocking applic ations using smbus, pmbus, or i 2 c interface, which is designed to be conflict free with cpu?s svid bus. this hybrid digital approach eliminates the need of nvm and firmware often seen in a full digital solution and significantly reduces design complexity, inventory and manufacturing costs. the ISL6381 utilizes intersil?s proprietary enhanced active pulse positioning (eapp) modulation sc heme to achieve the extremely fast transient response with fewer output capacitors. the ISL6381 accurately monitors the load current via the imon pin and reports this information via the i out register to the microprocessor, which sends a psi# signal to the controller at low power mode via svid bus. the controller enters 1- or 2-phase operation in low power mode (psi1); in the ultra low power mode (psi2, psi3), it oper ates in single phase with diode emulation option. in low power modes, the magnetic core and switching losses are significantly reduced, yielding high efficiency at light load. after the psi# signal is deasserted, the dropped phase(s) are added back to sustain heavy load transient response and efficiency. in addition, the ISL6381 features auto-phase shedding to optimize the efficiency from light to full load for green environment without sacrificing the transient performance. today?s microprocessors require a tightly regulated output voltage position versus load current (droop). the ISL6381 senses the output current continuously by measuring the voltage across a dedicated current sense resistor or the dcr of the output inductor. the sensed current flows out of the fb pin to develop the precision voltage drop across the feedback resistor for droop control. current sensing circuits also provide the needed signals for channel-current balancing, av erage overcurrent protection and individual phase current limiting. the tm pin senses an ntc thermistor?s temperature, which is internally digitized for thermal monitoring and for integrated thermal compensation of the current sense elements of the regulator. the ISL6381 features remote voltage sensing and completely eliminates any potential difference between remote and local grounds. this improves regulati on and protection accuracy. the threshold-sensitive enable input is available to accurately coordinate the start-up of the ISL6381 with other voltage rails. features ? intel vr12.5/vr12 compliant - serialvid with programmable imax, tmax, boot, address offset registers - vr12.5 core and vr12/vr12.5 memory ? intersil?s proprietary eapp hybrid digital enhanced active pulse positioning (eapp) modulation scheme (patented) - smbus/pmbus/i 2 c interface with svid conflict free - nvm and firmware free for low cost and easy use - auto phase shedding option for greener environment - variable frequency control du ring load transients to reduce beat frequency oscillation - linear control with evenly distributed pwm pulses for better phase current balance during load transients - voltage feed-forward and ramp adjustable options - high frequency and psi compensation options - proprietary active phase adding and dropping with diode emulation scheme for enhanced light load efficiency ? 1 to 4-phase with phas e doubler compatibility ? differential remote voltage sensing ? 0.5% closed-loop system accuracy over load, line and temperature ? programmable 1 or 2-phase operation in psi1 mode ? programmable slew rate of fast dynamic vid with dynamic vid compensation (dvc) ? droop and diode emulation options ? precision resistor or dcr differential current sensing - integrated programmable current sense resistors - accurate load-line (droop) programming - accurate current monitoring and channel-current balancing ? true catastrophic failure protection (cfp) ? average overcurrent protection and channel current limit with internal current comparators ? precision overcurrent pr otection on imon pin ? output voltage open sensing protection ? protection disable option ? accurate load-line (droop) programming ? up to 2mhz per phase ? thermal monitoring and integrated compensation ? start-up into precharged load ? pb-free (rohs compliant) ? 40 ld 5x5 tqfn june 12, 2014 fn8576.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL6381 2 fn8576.1 june 12, 2014 confidential submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 driver recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ISL6381 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application: 4-phase core vr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical application: 4-phase memory vr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functional pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multiphase power conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pwm modulation scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pwm and psi# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 diode emulation operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 channel-current balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 load-line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dynamic vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 operation initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 current sense output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 fault monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vr_ready signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 thermal monitoring (vr_hot#) and protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 temperature compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 integrated temperature compensa tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 design procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 external temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 hard-wired registers (patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 high frequency compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 dynamic vid compensation (dvc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 catastrophic fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 input current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 auto-phase shedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 svid operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 smbus, pmbus, and i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 general design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 current sensing resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 load-line regulation resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 output filter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ISL6381 3 fn8576.1 june 12, 2014 confidential submit document feedback layout and design considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 pin noise sensitivity, design and layout consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 powering up and open-loop test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 voltage regulator (vr) design materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ISL6381 4 fn8576.1 june 12, 2014 confidential submit document feedback pin configuration ISL6381 (40 ld 5x5 tqfn) top view ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6381crtz ISL6381 crtz 0 to +70 40 ld 5x5 tqfn l40.5x5 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for more information on msl, please see tech brief tb363. isen3+ isen3- isen1+ isen1- 1 2 3 4 5 6 7 8 9 10 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 40 39 38 37 isen4+ isen4- isen2+ isen2- open icl_spdupc_k pwm3 vr_rdy vr_hot# pwm1 pwm4 pwm2 vdband_pmadr_vrsel vcc fs_fdvid en_pwr_cfp rgnd vsen hfcomp psicomp fb comp svalert# svclk gnd 11 12 21 22 23 24 rset sm_pm_i2data tmx_drp_de_tc sm_pm_i2clk tm_en_otp isenin+ isenin- svdata imon imadr_btrm dvc_mem auto_npsi
ISL6381 5 fn8576.1 june 12, 2014 confidential submit document feedback driver recommendation driver quiescent current (ma) gate drive voltage # of drivers diode emulation (de) gate drive drop (gvot) comments isl6627 1.0 5v single yes no for psi# channel (and its coupled channel in coupled inductor applicat ions) or all channels. isl6620 isl6620a 1.2 5v single yes no for psi# channel (and its coupled channel in coupled inductor applicat ions) or all channels. shorter body diode conduction time when entering psi2 mode at a fixed voltage. isl6596 0.19 5v single no no for dropped phases or all channels without de. isl6610 isl6610a 0.24 5v dual no no for dropped phases or all channels without de. isl6611a 1.25 5v dual no no phase doubler with integrated drivers, up to 12-phase. for all channels with de disabled. isl6617 5.0 n/a n/a no no pwm doubler for drmos, up to 12- or 24-phase. for all channels with de disabled. isl6622 5.5 12v single yes yes for psi# channel (and its coupled channel in coupled inductor applicat ions) or all channels. shorter body diode conduction time when entering psi2 mode at a fixed voltage. isl6622a isl6622b 5.5 12v single yes no yes for psi# channel (and its coupled channel in coupled inductor applicat ions) or all channels. shorter body diode conduction time when entering psi2 mode at a fixed voltage. note: intersil 5v and 12v drivers are mostly pin-to-pin compatible and allow for dual footprint layout implementation to optimiz e mosfet selection and efficiency. the 5v drivers are more suitable for hi gh frequency and high power density applications.
ISL6381 6 fn8576.1 june 12, 2014 confidential submit document feedback ISL6381 internal block diagram ref fb vr_hot# temperature compensation isen1+ isen1- isen2+ isen2- isen3+ isen3- isen4+ isen4- ? channel current balance and peak current limit 0.85v - + power-on reset (por) - + n n gnd pwm2 pwm1 pwm3 pwm4 temperature compensation gain adjust eapp modulator eapp modulator eapp modulator eapp modulator rgnd svclk svalert# svdata - + e/a tmax vsen comp hfcomp high frequency compensation psicomp psi# 1 n i_trip - + ocp vr_rdy imon 3.0v tcomp tm_en_otp tcomp fs_fdvid vr0: clock and ramp generator soft-start and fault logic psi# vcc thg idroop idroop - + ocp rset shed reset latch thermal monitor and protection tmax + + sm_pm_i2data sm_pm_i2clk svid bus interface dac and offset - + ovp + - 175mv smbus/ pmbus/i 2 c interface channel detect imadr_btrm isenin- iin input current monitor isenin+ iin en_pwr_cfp iin_trip - + ocp dvc x4/3 thg thg tm_en auto phase shedding auto_npsi shed channel current sense tmx_drp_de_tc otp otp band_pmadr_vrsel icl_spdupc_k
ISL6381 7 fn8576.1 june 12, 2014 confidential submit document feedback typical application: 4-phase core vr vcc imon vsen rgnd svdata vr_rdy rset cpu load vinf en_pwr_cfp ISL6381 +5v sm_pm_i2da vr_hot# isen1- isen1+ pwm1 +5v vcc pwm boot ugate phase lgate gnd isl6627 driver isen2- isen2+ pwm2 +5v vcc pwm boot ugate phase lgate gnd isl6627 driver isen4- isen4+ pwm4 +5v vcc pwm boot ugate phase lgate gnd vinf isl6627 driver svclk svalert# fs_fdvid hfcomp isen3- isen3+ pwm3 vinf ntc: beta = 3477 vin vinf vinf isenin+ isenin- r isenin1 tm_en_otp vcc ntc r isenin2 psicomp fb dvc_mem comp cfp r senin auto_npsi sm_pm_i2clk gnd imadr_btrm vcc tmx_drp_de_tc 4x vdband_pmadr_vrsel vcc icl_spdupc_k
ISL6381 8 fn8576.1 june 12, 2014 confidential submit document feedback typical application: 4-phase memory vr vcc imon vsen rgnd svdata vr_rdy rset cpu load vinf en_pwr_cfp ISL6381 +5v sm_pm_i2da vr_hot# isen1- isen1+ pwm1 +5v vcc pwm boot ugate phase lgate gnd isl6627 driver isen2- isen2+ pwm2 +5v vcc pwm boot ugate phase lgate gnd isl6627 driver isen4- isen4+ pwm4 +5v vcc pwm boot ugate phase lgate gnd vinf isl6627 driver svclk svalert# fs_fdvid psicomp isen3- isen3+ pwm3 vinf ntc: beta = 3477; must be placed on phase#1 output inductor end (see figure 24) vin vinf vinf isenin+ isenin- r isenin1 tm_en_otp vcc ntc r isenin2 hfcomp fb dvc_mem comp cfp r senin auto_npsi sm_pm_i2clk gnd imadr_btrm vcc tmx_drp_de_tc 4x vdband_pmadr_vrsel sm_pmalert# vcc vcc icl_spdupc_k
ISL6381 9 fn8576.1 june 12, 2014 confidential submit document feedback absolute maximum rating s thermal information vcc, vr_rdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6v isenin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd -0.3v to 27v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd -0.3v to v cc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5kv charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250v recommended operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% ambient temperature ISL6381crtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c thermal resistance ( notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 40 ld 5x5 tqfn package . . . . . . . . . . . . . . 31 2.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, v cc = 5v, unless otherwise specified. boldface limits apply over the operating temperature range. parameter test conditions min ( note 7 )typ max ( note 7 )units vcc supply current nominal supply v cc = 5vdc; en_pwr = 5vdc; r t = 125k ?? isen1-4 = 0a 18 22 24 ma shutdown supply v cc = 5vdc; en_pwr = 0vdc; r t = 125k 14 18 21 ma power-on reset and enable v cc rising por threshold 4.30 4.40 4.50 v v cc falling por threshold 4.00 4.11 4.20 v en_pwr_cfp high level turn-off threshold externally driven 3.55 3.63 3.70 v en_pwr_cfp high level turn-on threshold externally driven 3.33 3.47 3.53 v en_pwr_cfp latch-off level internally driven, 5ma load 4.80 v en_pwr_cfp internal pull-up impedance 12 34 en_pwr_cfp rising threshold 0.830 0.850 0.870 v en_pwr_cfp falling threshold 0.730 0.750 0.770 v dac (vid+offset) system accuracy of ISL6381crtz (dac = 1.5v to 3.04 v, t j = 0c to +70c) ( note 6 , closed-loop) -0.5 - 0.5 %vid system accuracy of ISL6381crtz (dac = 0.8v to 1.49v, t j = 0c to +70c) ( note 6 , closed-loop) -5 - 5 mv system accuracy of ISL6381crtz (dac = 0.25v to 0.795v, t j = 0c to +70c) ( note 6 , closed-loop) -8 - 8 mv oscillators accuracy of switching frequency setting r fs = 125k 360 400 440 khz maximum switching frequency 2.0 mhz minimum switching frequency 0.08 mhz
ISL6381 10 fn8576.1 june 12, 2014 confidential submit document feedback soft-start ramp rate fdvid = 10mv/s 2.5 2.75 3.2 mv/s fdvid = 20mv/s 5.0 5.5 6.0 mv/s fast dynamic vid slew rate range programmable via pmbus 10 53 mv/s maximum duty cycle per pwm 400khz 95 98 99 % pwm generator ( note 7 ) sawtooth amplitude vr ramp_adj = 1.2v; isenin+ = 12v 1.2 v vr ramp_adj = 1.5v; isenin+ = 12v 1.5 v maximum adjustable ramp via pmbus or pin 1.5 v minimum adjustable ramp via pmbus 0.75 v error amplifier open-loop gain r l = 10k to ground 96 db open-loop bandwidth 80 mhz slew rate 25 v/s maximum output voltage no load 4.1 4.4 v output high voltage 1ma load 3.8 4.1 v output low voltage 1ma load 0.85 1.00 1.50 v pwm output (pwm[4:1] pwm[4:1] sink impedance pwm = low with 1ma, load for fast transition 80 pwm = low with 1ma load 190 285 410 pwm[4:1] source impedance pwm = high, forced to 3.7v 95 125 175 pwm psi1/2/3/decay mid-level 0.4ma load 36 40 44 %vcc current sense and overcurrent protection sensed current tolerance isen1-4 = 40a; cs offset and mirror error included, r set = 12.8k 37 40 43.5 a isen1-4 = 80a; cs offset and mirror error included, r set = 12.8k 76 80 84 a average overcurrent trip level at normal ccm pwm mode cs offset and mirror error included, r set = 12.8k 94 100 106 a average overcurrent trip level at psi1/2/3 mode n = 4 drop to 1-phase 96 108 121 a average overcurrent trip level at psi1 mode n = 4 drop to 2-phase 91 103 113 a peak current limit for individual channel 125 a imon ocp trip level 2.9 3.0 3.1 v imon voltage imax (ff) trip poin t higher than this will be ?ff? 2.45 2.5 2.56 v read_iin (1f) maximum threshold 10 a input peak current trip level 14 15 16 a maximum common mode input vcc-1.5v thermal monitoring vr_hot# pull-down impedance 7 13 tm voltage at thermal trip (programmable via tmax) tmax = +100c, (see table 7 ) 39.12 %vcc electrical specifications recommended operating conditions, v cc = 5v, unless otherwise specified. boldface limits apply over the operating temperature range. (continued) parameter test conditions min ( note 7 )typ max ( note 7 )units
ISL6381 11 fn8576.1 june 12, 2014 confidential submit document feedback vr_hot# and thermal alert# hysteresis 3c leakage current of vr_hot# with extern al pull-up resistor connected to v cc 1 a tm_en_otp shutdown threshold 0.85 0.95 1.05 v tm_en_otp turn-on threshold 0.98 1.08 1.18 v vr ready and protection monitors leakage current of vr_rdy with pull-up resistor externally connected to v cc 1 a vr ready low voltage 4ma load 0.3 v overvoltage protection threshold prior to the end of soft-start 2.15 v after the end of soft-start, the voltage above vid 175 mv after the end of soft-start, the voltage above vid 350 mv overvoltage protection reset hysteresis 100 mv svid bus alert# pull-down impedance 7 13 svdata 7 13 svclk maximum speed at room temperature t j = +25c 60 mhz svclk maximum speed 43 mhz svclk minimum speed 13 mhz smbus/pmbus/i 2 c data pull-down impedance 28 40 clock maximum speed 1.5 mhz clock minimum speed 0.05 mhz timeout 25 32 35 ms notes: 6. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications recommended operating conditions, v cc = 5v, unless otherwise specified. boldface limits apply over the operating temperature range. (continued) parameter test conditions min ( note 7 )typ max ( note 7 )units
ISL6381 12 fn8576.1 june 12, 2014 confidential submit document feedback functional pin descriptions refer to table 25 on page 48 , for design and layout considerations. vcc - supplies the power necessary to operate the chip. the controller starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. connect this pin directly to a +5v supply with a high quality ceramic bypass capacitor. gnd - the bottom metal base of ISL6381 is the gnd, bias and reference ground for the ic. it is also the return for all pwm output drivers. en_pwr_cfp - this pin is a threshold-sensitive enable input and a catastrophic failure protection (cfp) output for controller. connecting the power train input supply to this through an appropriate resistor divider prov ides a means to synchronize the power sequencing of the controll er and the mosfet driver ics. when en_pwr_cfp is driven above 0.85v but below 3.3v, the controller is actively depending on status of the tm_en_otp, the internal por, and pending fault states. driving en_pwr_cfp below 0.75v will turn off the controller, clear all fault states (except for cfp latch up) and prep are the ISL6381 to soft-start when re-enabled. in addition, this pin will be latched high (vcc) by the input overcurrent event (monitored by isenin) or vr overvoltage event. the latch resets by cycling vcc and cannot reset by tm_en_otp or en_pwr_cfp since when the catastrophic failure (cfp) is triggered, the power is removed from vr so is the vtt voltage rail and its pgood signal. this feature means to provide protection to the case that the shorted high-side mosfet vr draws insufficient current to trigger the input supply?s over current trip level, this pin will send an active high signal (cfp) to disconnect the input supply before catching fire. when this pin is driven above 3.7v externally, the controller turns off. vsen - this pin monitors the regulator output for overvoltage protection. connect this pin to the positive rail remote sensing point of the microprocessor or load. this pin tracks with the fb pin. if a resistive divider is placed on the fb pin, a resistive divider with the same ratio should be plac ed on the vsen pin. tie to gnd if not used. rgnd - this pin compensates the offset between the remote ground of the load and the local ground of this device. connect this pin to the negative rail remote sensing point of the microprocessor or load. tie to gnd if not used. comp and fb - the comp and fb are the output and inverting input of the precision error amplif ier, respectively. a type iii loop compensation network should be connected to these pins, while the fb?s r-c network should conne ct to the positive rail remote sensing point of the microprocessor or load. combined with rgnd, the potential difference between remote and local rails is completely compensated for and it improves regulation accuracy. a properly chosen resistor between fb and remote sensing point can set the load-line (droop, if enabled). the droop scale factor is set by the ratio of the effective isen resistors (set by rset) and the inductor dcr or the dedicated current sense resistor. the comp is tied back to fb through an external r-c network to compensate the regulator. an rc from the fb pin to ground is needed if the output is lagging from the dac, typical of applications with many output capacitors and droop enabled. vr_rdy _ vr_rdy indicates that soft-start has completed and the output remains in normal operat ion. it is an open-drain logic output. when ocp or ovp occurs, vr_rdy is pulled low. tm_en_otp - the input pin for the temperature measurement. connect this pin through an ntc th ermistor to gnd and a resistor to vcc of the controller. the voltage at this pin is inversely proportional to the vr temperatur e. the device monitors the vr temperature based on the voltage at the tm pin. combined with the ?tcomp? setting, the sensed current is thermally compensated. the vr_hot# asserts low if the sensed temperature at this pin is higher than the maximum desired temperature, ?tmax?. the ntc should be placed close to the current sensing element, the output inductor or dedicated sense resistor on phase 1. a decoupling capacitor (0.1f) is typically needed in close proximity to the controller. in addition, the controller is disabled when this pin?s voltage drops below 0.95 (typically) and is active when it is above 1.08v (typically); it can serve as enable and over-temperature functions, however, when it is used as an enable toggle input, bit2 of status_byte (78h) will flag ot; clear_faults ( 03h) command must be sent to clear the fault after vr start-up. if not used, connect a 1m /2m resistor divider or tie to vcc. vr_hot# - indicator of high vr temperature. it is an open-drain logic output. normally open if the measured vr temperature is less than a certain level, and pulled low when the measured vr temperature reaches a certain level. pwm[4:1] - pulse width modulation outputs. connect these pins to the pwm input pins of the intersil driver ic(s). the number of active channels is determined by the state of pwm[4:2]. tie pwm(n+1) to vcc to configure for n-phase operation. the pwm firing order is sequential from 1 to n with n being the number of active phases. if pwm1 is tied high, the respective address is released for use, i.e, the vr is disabled and does not respond to the svid commands. isen[4:1]+, isen[4:1] - the isen+ and isen- pins are current sense inputs to individual differential amplifiers of vr. the sensed current is used for channel current balancing, overcurrent protection, and droop regulation. inactive channels should have their respective current sense in puts, isen[4:#]- grounded, and isen[4:#]+ open. for example, ground isen[4:3]- and open isen[4:3]+ for 2-phase operatio n. do not ground isen[4:1]+. for dcr sensing, connect each isen- pin to the node between the rc sense elements. tie the isen+ pin to the other end of the sense capacitor (typically output rail). the voltage across the sense capacitor is proportional to the inductor current. therefore, the sensed current is proportion al to the inductor current and scaled by the dcr of the inductor and r set . rset- a resistor connected from this pin to ground sets the current gain of the current sensing amplifier. the r set resistor value can be set from 3.84k ? to 60.4k ? and is 64x of the equivalent r isen resistor value. therefore, the effective current sense resistor value can be set between 60 ? and 943 ? . imon - mon is the output pin of sens ed, thermally compensated (if internal thermal compensation is used) average current of vr. the voltage at the imon pin is proportional to the load current and the
ISL6381 13 fn8576.1 june 12, 2014 confidential submit document feedback resistor value. when it reaches to 3.0v, it initiates an overcurrent shutdown, while 2.5v imon voltage corresponds to i out (15h) of ffh reading. by choosing the proper va lue for the resistor at imon pin, the overcurrent trip level can be set lower than the fixed internal overcurrent threshold. during dynamic vid, the ocp function of this pin is disabled to avoid false triggering. tie it to gnd if not used. see ? current sense output ? on page 25 for more details. auto_npsi - a paralleling resistor and capacitor from the pin to ground sets the current threshold and hysteresis of phase dropping. the auto mode can be disabled by pulling this pin to ground or vcc. this pin also sets the operating phase number option (npsi) in low power mode. see table 3 on page 16 on and table 14 on page 35 for more details. fs_fdvid - a resistor placed from this pin to gnd/vcc will set the switching frequency. the rela tionship between the resistor value of the resistor and the switching frequency is approximated by equation 4 on page 16 . when the resistor is connected to gnd, it sets the fast dynamic vid rate 20mv/s for v core mode (dvc_mem = rc or open); 10mv/s for memory mode (dvc_mem = v cc ); when the resistor is connected to v cc , it sets the fast dynamic vid rate 10mv/s, typically used for desktop applications. hfcomp - connect a resistor of the same or slightly higher (~ 150%) value as the feedback impedance (r fb ) to the vr output to compensate the level-shifted output voltage during high-frequency load transient events. connecting more than 3x of r fb to this pin virtually disables this feature. when the droop disabled, an additional 499k (typically) from this pin to vcc, as shown in figure 29 , to ensure proper vr operation when the integrator capacitance from comp to fb is too low (typically less than 68pf). psicomp - connect a series rc across the type iii compensation network of the vr output voltage. this improves loop gain and load transient response in psi1 /2/3/decay mode. an open pin disables this feature. dvc_mem - a series resistor and ca pacitor can be connected from this pin to the fb pin to compensate and smooth dynamic vid transitions. when this pin tied to vcc, the dvid rate will be default at 10mv/s independent of fs_dvid pin, while boot voltages (see bt) are set fo r memory applications and vdband_pmadr_vrsel become s a programming pin for vdband, pmbus address offset and vr12/vr12.5 mode selection. when this pin is not tied to vcc (open or rc), it can program vdband, but not pmadr or vrsel (see table 10 for more details). svclk - synchronous clock signal input of serialvid bus from cpu. svdata - i / o pin for transferring data signals between cpu and vr controller. svalert# - output pin for transferring the active low signal driven asynchronously from the vr controller to cpu. isenin+, isenin - these pins are current sense inputs to the differential amplifier of the input supply. the sensed current is used for input power monitoring and power management of the system. the resistor sensing is typically recommended. for dcr sensing, connect each isenin pi n to the node between the rc sense elements. tie the isenin- pin to the other end of the sense capacitor through a resistor, r isenin . the voltage across the sense capacitor is proportional to the inductor current. therefore, the sense current is proportional to the inductor current and scaled by the dcr of the inductor and r isenin . in addition, if the 15a comparator is triggered, it will see it as the catastrophic failure and pull the en_pwr_cfp pin vcc to signal the system for protection. when not used, connect isenin+ to vin and a resistor divider with a ratio of 1/ 3 on isenin pins (for instance, 499k in between isenin pins and then 1.5m from isenin- to ground (see figure 34 ). refer to ? input current sensing ? on page 34 for proper configuration de tails. furthermore, isenin+ should be connected to the input voltage (vin) for feed-forward compensation to maintain a constant loop gain over the input line variation. do not leave the isenin+ pin open. sm_pm_i2clk - synchronous clock signal input of smbus/pmbus/i 2 c. sm_pm_i2data - i / o pin for transferring data signals smbus/pmbus/i 2 c and vr controller. open - keep this pin floating. imadr_btrm, tmx_drp_de_tc, vdband_pmadr_vrsel, icl_spdupc_k - register pins used to program system parameters. they can be read back via 0c, 0d, 0e, 0f in svid or dc, dd, de, b0 via smbus/pmbus/i 2 c, respectively. their functionalities are described in the following; refer to table 10 , ? system parameter description ? on page 31 on for summary. imadr_btrm (imax_addr_bt_ramp, reg. 0c/dc) - imax maximum current, i ccmax , register of the voltage regulator. it has a range of 0a to 255a with 1a/step on independent register da while programmed by the pmbus/smbus/i 2 c, otherwise, it has limited choices based upon operating phase number listed in table 11 . this register represents the maximum allowed load current for vr and corresponds to a 2.5v (typically set) at imon. addr - svid and smbus/pmbus/i 2 c address offset register of vr: 0/80, 0/82, 0/84, 0/86 (svid/pmbus) when dvc_mem is open or an rc to fb pin; 2, 4, 6, 8 (svid) when dvc_mem tied to vcc. e/f is an all call address for svid. bt - start-up boot voltage register of vr. when the dvc_mem pin is open or connects an rc to fb pin, the boot voltages are: 0v, 1.65v, 1.70v, and 1.75v for core applications where svid is compliant with vr12.5. when the dvc_mem pin is tied to vcc, the boot levels are changed to 0v, 1.2v, 1.35v, and 1.5v for memory applications and where sv id protocol is compliant with vr12 or vr12.5 selectable vi a the vdband_pmadr_vrsel pin. ramp - get feed-forward ramp (1.2v or 1.5v). tmx_drp_de_tc (tmax_drp_de_t comp, reg. 0d/dd) - tmax maximum temperature register (tmax) of the vr and the thermal trip point of vr_hot#. it covers +85c to +120c with +5c/step. the register represents the maximum allowed temperature of vr, and programs the over-temperature trip point at vr_hot#. the typical application should use a setting of +100c or lower, since the ntc thermistor temperature represents the pcb, not the hottest component on the board. in addition, the ntc thermistor typically
ISL6381 14 fn8576.1 june 12, 2014 confidential submit document feedback picks up a temperature lower than the pcb due to the thermal impedance between pcb and ntc. drp - select the droop enable or disable of vr. de - diode emulation (de) operation register of vr in psi2, psi3, and decay modes. in psi1 mode, the vr always operates in ccm mode. when diode emulation is disabled, the output decays at the rate of setvid slow; however, the svid bus still acknowledges execution of the command. tcomp - temperature differential (-2.5c to +29.7c) between the actual sensed inductor of the vr regulator and the ntc thermistor at the tm pin. the voltage sensed on the tm pin is utilized as the temperature input to adjust the droop current and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element of vr. to implement the integrated temperature compensation, select a proper temperature offset ?tcomp,? othe r than the ?off? value, which disables the integrated temper ature compensation function. vdband_padr_vrsel (available dvc_mem = vcc, 0e/de) vdband - select comp ripple voltage band, to control speed up. padr (pmaddr) - it sets smbus/pmbus/i 2 c 16 independent address offset (e0 to ee, c8 to ce, 88 to 8e) when dvc_mem is tied to vcc for memory applications. vrsel - when dvc_mem is tied to vcc, this pin allows selection of vr12 or vr12.5 vid code for memory applications. icl_spdupc_k (reg of/bo) icl - it sets the cycle-by-cycle overcurrent limit, independently for each channel. it also adds on top of the level programmed by f4h. this current will be used as reference and compared with the sensed peak current to detect over current condition. it ranges from 70a to 125a. spdupc - select the sensitivity of speed up control. it has selection values ranging from 2pf to 16pf (2pf/step, no 14pf selection), and original. k - select?s comp voltage clamp control threshold, which will determine how close it should be to the targeted comp voltage before starting pwm pulse. operation the ISL6381 is a 4-phase pwm controller for microprocessor vr12.5 core and up to 4-phase for vr12/vr12.5 memory voltage regulator. the ISL6381 is designed to be compliant to intel vr12.5/vr12 specifications with serialvid features. the smbus/pmbus/i 2 c can be programmed with embedded controller. the system parameters and svid required registers are programmable with two dedicated pins in ISL6381. this greatly simplifies the system design for various platforms and lowers inventory complexity and cost by using a single device. in addition, this controller is compatible with phase doublers (isl6611a and isl6617), which can double or quadruple the phase count. for instance, the multi-phase pwm can realize up to 16-phase count system. a higher phase count system can improve thermal distribution and powe r conversion efficiency at heavy load. multiphase power conversion microprocessor load current profiles have changed to the point that the advantages of mult iphase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter (which are both cost-effective and thermally viable), have forced a change to the cost-saving approach of multiphase. the ISL6381 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. the typical application circuit diagrams on page 7 and page 8 provide the top level views of multiphase power conversion using the ISL6381 controller. interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with each of the other channels. in a 3-phase converter, each chan nel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the 3-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase, as illustrated in figure 1 . the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple componen t has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the dc components of th e inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multiphase circuit, examine equation 1 , which represents an individual channel?s peak-to-peak inductor current. in equation 1 , v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. in the case of multiphase converters, the capacitor current is the sum of the ripple currents from ea ch of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 2 , the peak-to-peak overall ripple current (i c,pp ) decreases with the increase in the number of i pp v in v out ? ?? v out ? lf sw v ? in ? --------------------------------------------------------- - = (eq. 1) figure 1. pwm and inductor-current waveforms for 3-phase converter 1s/div pwm3, 5v/div pwm2, 5v/div il3, 7a/div il2, 7a/div il1 + il2 + il3, 7a/div il1, 7a/div pwm1, 5v/div
ISL6381 15 fn8576.1 june 12, 2014 confidential submit document feedback channels, as shown in figure 2 . output voltage ripple is a func tion of capacitance, capacitor equivalent series resistance (e sr), and the summed inductor ripple current. increased ripple frequency and lower ripple amplitude mean that the desi gner can use less per channel inductance and few or less costly output capacitors for any performance specification. another benefit of interleaving is to reduce the input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lowe ring input ripple current and allowing the designer to reduce the cost of input capacitors. the example in figure 3 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 3 delivers 36a to a 1.5v load from a 12v input. the rms input capacitor current is 5.9a. compare this to a single-phase converter also st epping down 12v to 1.5v at 36a. the single-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. figures 42 , 43 and 44 , as described in the ? input capacitor selection ? on page 47 , can be used to determine the input capacitor rms current based on load current, duty cycle, and the number of channels. they are pr ovided as aids in determining the optimal input capacitor solution. figure 45 shows the single phase input-capacitor rms current for comparison. pwm modulation scheme the ISL6381 adopts intersil's proprietary enhanced active pulse positioning (eapp) modulation scheme to improve transient performance. the eapp is a unique dual-edge pwm modulation scheme with both pwm leading and trailing edges being independently moved to give the best response to transient loads. the eapp has an inherited function, similar to intersil's proprietary adaptive phase alignment (apa) technique, to turn on all phases together to furthe r improve the transient response, when there are sufficiently large load step currents. the eapp is a variable frequency architecture , providing linear control over transient events and evenly distributing the pulses among all phases to achieve very good current balance and eliminate beat frequency oscillation over a wi de range of load transient frequencies. to further improve the line and load transient responses, the multi-phase pwm features feed-forward function to change the up ramp with the input line (isenin+ input) to maintain a constant overall loop gain over a wide range input voltage. the up ramp of the internal sawtooth is defined in equation 3 , where v upramp is programmable by ?rm? register pin and smbus/pmbus/i 2 c. with eapp control and feed-forward function, the ISL6381 can achieve excellent transient performance over wide frequency range of load step, resulting in lower demand on the output capacitors. at dc load conditions, the pwm frequency is constant and set by the external resistor between th e fs pin and gnd during normal mode (psi0) and low power mode (psi1). however, when psi2 or psi3 is asserted in ultra low power conditions, if the vr is (eq. 2) m roundup n d ? 0 ? ?? = for m1 ? nd ? m ?? i cpp , v out lf sw ? -------------------- k rcm = k rcm nd ? m ? 1 + ?? mnd ? ?? ? ?? ? nd ? ---------------------------------------------------------------------------- - = duty cycle (v out /v in ) figure 2. ripple current multiplier vs. duty cycle ripple current multiplier, k rcm n = 1 3 4 2 5 6 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 70 80 90 100 figure 3. channel input currents and input-capacitor rms current for 3-phase converter channel2input current 10a/div channel 3 input current 10a/div channel 1 input current 10a/div input-capacitor current, 10a/div 1s/div (eq. 3) v ramp v in v ? upramp 12v ------------------------------------------ - =
ISL6381 16 fn8576.1 june 12, 2014 confidential submit document feedback configured for diode emulation operation, the eapp reduces the switching frequency as the load decreases. thus, the vr can enter burst mode at extreme light load conditions and improve power conversion efficiency significantly. under steady state conditions, the operation of the ISL6381 pwm modulator is similar to a conventional trailing edge modulator. conventional analysis and design methods can therefore be used for steady st ate and small signal analysis. pwm and psi# operation the timing of each channel is set by the number of active channels. the default channel setting for the ISL6381 is four. the switching cycle is defined as the time between pwm pulse termination signals of each channel. the cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the fs pin and ground. the pwm signals command the mosfet driver to turn on/off the channel mosfets. the ISL6381 can work in a 0 to 4-phase configuration. tie pwm(n+1) to vcc to configure fo r n-phase operation, and leave other higher order pwm (>n+1) open. pwm firing order is sequential from 1 to n with n being the number of active phases, as summarized in table 1 . for 4-phase operation, the channel firing sequence is 1-2-3-4, and they are evenly spaced over 1/4 of a cycle. connecting pwm4 to vcc configures 3-phase operation; the channel firing order is 1-2-3 and the phase spacing is 1/3 of a cycle. if pwm2 is connected to vcc, only channel 1 operation is selected. if pwm1 is connected to vcc, the vr operation is turned off. for memory applications, the dvc_mem pin should be tied to vcc, the vdband_pmadr _vrsel pin becomes a register pin to program vr12 or vr12.5 mode and smbus/pmbus/i 2 c addresses. the cpu can enter four distinct power states, as shown in table 2 . the ISL6381 supports all states, but it treats psi2 and psi3 the same. in addition, the setdecay mode will automatically enter psi2 state while the output voltage decaying. however, prior to the end of soft-start (i.e: vr_rdy goes high), the lower power modes (psi1/2/3/decay) are not enabled. when the svid bus sends psi1/2/3 or set vid decay command, it indicates the low power mode operation of the processor. the controller starts phase shedding the next switching cycle. the controller reduces the number of active phases according to the logic on table 3 . ?npsi? register programs the controller number of phases operation in psi1 mode. when psi1 is asserted, vr is in single-phase ccm operation with pwm1, or 2-phase ccm operation with pwm1 and 2, 3 or 4, as shown in table 1 . the number of oper ational phases is configured by ?npsi? register, as shown in table 3 . in psi2/3/decay state, only pwm1 is in dcm/ccm operation, which is programmed by the ?de? register. while the controller is operational (v cc above por, tm_en_otp and en_pwr are both high, valid vi d inputs), it can pull the pwm pins to ~40% of v cc (~2v for 5v vcc bias) during various stages, such as soft-start delay, phase shedding operation, or fault conditions (oc or ov events). the matching driver's internal pwm resistor divider can further raise the pwm potential, but not lower it below the level set by the controller ic. therefore, the controller's pwm outputs are directly compatible with intersil drivers that require 5v pwm signal amplitudes. drivers requiring 3.3v pwm signal amplitudes are generally incompatible. diode emulation operation to improve light efficiency, the ISL6381 can enter diode emulation operat ion in psi2/3 or decay mode. users should select intersil vr12/vr12.5 comp atible drivers: the isl6627 or isl6622 for psi# channel(s). th e diode emulation should be disabled when non-compatible power stages or drivers are used. switching frequency the vr?s switching frequency is determined by the selection of the frequency-setting resistor, r t , which is connected from fs_fdvid pin to gnd or vcc. equation 4 and figure 4 are provided to assist in selectin g the correct resistor value. where f sw is the switching frequency of each phase. table 1. phase number and pwm firing sequence n phase sequence psi# = psi0 pwm# tied to v cc (vcore) pwm# tied to v cc (memory) active phase psi# = psi1 4 1-2-3-4 x_mem = v cc pwm1/3 3 1-2-3 pwm4 pwm4 pwm1/2 2 1-2 pwm3 pwm3 pwm1/2 1 1 pwm2 pwm2 pwm1 table 2. power state command from cpu state description psi0 high power mode; all phases are running psi1 low power mode psi2 very low power mode psi3 ultra low power mode, treated as psi2 decay automatically enter psi2 an d ramp down the output voltage reference to the target voltage table 3. phase dropping configuration at psi1 and psi2/3/decay npsi code psi1 mode psi2/3 and decay si1 1-phase 1-phase si2 2-phase 1-phase (eq. 4) r t 510 ? 10 f sw -------------------- =
ISL6381 17 fn8576.1 june 12, 2014 confidential submit document feedback current sensing the ISL6381 senses current contin uously for fast response. the ISL6381 supports inductor dcr sensing, or resistive sensing techniques. the associated channel current sense amplifier uses the isen inputs to reproduce a sign al proportional to the inductor current, i l . the sense current, i sen , is proportional to the inductor current. the sensed current is used for current balance, load-line regulation, and overcurrent protection. the internal circuitry, shown in figures 5 and 6 , represents one channel of the vr output, respectively. the isen circuitry is repeated for each channel, but may not be active depending on the status of the pwm[4:2] pins, as described in ? pwm and psi# operation ? on page 16 . the input bias current of the current sensing amplifier is typically 20na; less than 10k ? input impedance is preferred to minimize the offset error, i.e., a larger c value as needed. inductor dcr sensing an inductor?s winding is characteri stic of a distributed resistance, as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 5 . the channel current i l , flowing through the inductor, will also pass through the dcr. equation 5 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across the inductor extracts the dcr voltage, as shown in figure 5 . the voltage on the capacitor v c , can be shown to be proportional to the channel current i l (see equation 6 ). if the r-c network components are selected such that the rc time constant matches the inductor time constant (r*c = l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e., proportional to the channel current. with the internal low-offset current amplifier, the capacitor voltage v c is replicated across the sense resistor r isen . therefore, the current out of the isen+ pin, i sen , is proportional to the inductor current. equation 7 shows that the ratio of the channel current to the sensed current, i sen , is driven by the value of the sense resistor and the dcr of the inductor. resistive sensing for more accurate current sensing, a dedicated current-sense resistor r sense in series with each output inductor can serve as the current sense element (see figure 6 ). this technique however reduces overall converter efficiency due to the additional power loss on the current sense element r sense . figure 4. switching frequency vs r t frequency-setting switching frequency (hz) 500 450 400 350 300 250 200 150 100 50 0 100 200 300 400 500 600 700 800 900 1000 resistor value (r, k ) v l s ?? i l sl dcr + ? ?? ? = (eq. 5) figure 5. dcr sensing configuration i n i sen i l dcr 64 ? r set ------------------------ - = - + isen-(n) current sense isen+(n) dcr l inductor r v out c out - + v c (s) c i l s ?? - + v l ISL6381 rset r isen(n) c t , optional v c s ?? s l dcr ------------- ? 1 + ?? ?? dcr i l ? ?? ? src 1 + ? ?? -------------------------------------------------------------------- - = (eq. 6) i sen i l dcr r isen ----------------- - ? i l dcr 64 ? r set ------------------------ - == (eq. 7)
ISL6381 18 fn8576.1 june 12, 2014 confidential submit document feedback a current sensing resistor has a distributed parasitic inductance, known as esl (equivalent series inductance, typically less than 1nh) parameter. consider the esl as a separate lumped quantity, as shown in figure 6 . the channel current i l , flowing through the inductor, will also pass through the esl. equation 8 shows the s-domain equivalent voltage across the resistor v r . a simple r-c network across the cu rrent sense resistor extracts the r sen voltage, as shown in figure 7 . the voltage on the capacitor v c , can be shown to be proportional to the channel current i l (see equation 9 ). if the r-c network components are selected such that the rc time constant matches the esl-r sen time constant (r*c = esl/r sen ), the voltage across the capacitor v c is equal to the voltage drop across the r sen , i.e., proportional to the channel current. as an example, a typical 1m sense resistor can use r = 348 and c = 820pf for the matching. figures 7 and 8 show the sensed waveforms without and with matching rc when using resistive sense. equation 10 shows that the ratio of the channel current to the sensed current, i sen , is driven by the value of the sense resistor and the r isen . however, the r isen resistor of each channel is integrated, while its value is determined by the r set resistor. the r set resistor value can be from 3.84k ? to 60.4k ? and is 64x the required i sen resistor value. therefore, the current sense gain resistor (integrated r isen ) value can be effectively set at 60 ?? to 943 ? . the inductor dcr value will increa se as the temperature increases. therefore, the sensed current will increase as the temperature of the current sense element increase s. in order to compensate the temperature effect on the sensed current signal, a negative temperature coefficient (ntc) resistor can be used for thermal compensation, or the integrat ed temperature compensation function of the ISL6381 should be utilized. the integrated temperature compensation function is described in ? temperature compensation ? on page 28 . decoupling capacitor (c t ) on isen[4:1]- pins are optional and might be required for long sense traces and a poor layout. l/dcr or esl/r sen matching assuming the compensator design is correct, figure 9 shows the expected load transient response waveforms if l/dcr or esl/r sen is matching the r-c time constant. when the load current i out has a square change, the output voltage v out also has a square response, except for the overshoot at load release. however, there is always some pcb contact impedance of current sensing components between the two current sensing points; it hardly accounts into the l/dcr or esl/r sen matching calculation. fine tuning the matching is necessarily done in the board level to improve overall transient performance and system reliability. if the r-c timing constant is too large or too small, v c (s) will not accurately represent real-time i out (s) and will worsen the transient response. figure 10 shows the load transient response when the r-c timing constant is too small. the v out will sag excessively upon load insertion and may create a system failure or early overcurrent trip. figure 11 shows the transient response when the r-c timing constant is too large. v out is sluggish in drooping to its final value. there will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the cpu reliability. figure 6. sense resistor in series with inductors i n i sen i l r sen 64 ? r set -------------------------- - = - + isen-(n) current sense isen+(n) ISL6381 rset r isen(n) r sen l v out c out i l r - + v c (s) c esl r sense - + v r c t , optional v r s ?? i l s esl r sen + ? ?? ? = (eq. 8) v c s ?? s esl r sen --------------- - ? 1 + ?? ?? r sen i l ? ?? ? src 1 + ? ?? ------------------------------------------------------------------------- = (eq. 9) figure 7. voltage across r without rc figure 8. voltage across c with matching rc i sen i l r sen r isen ----------------- - ? i l r sen 64 ? r set -------------------------- - == (eq. 10)
ISL6381 19 fn8576.1 june 12, 2014 confidential submit document feedback channel-current balance the sensed current i n from each active channel is summed together and divided by the number of active channels. the resulting average current i avg provides a measure of the total load current. channel current balance is achieved by comparing the sensed current of each cha nnel to the average current to make an appropriate adjustment to the pwm duty cycle of each channel with intersil?s patented current-balance method. in addition, the channel current or thermal balance can be adjusted via pmbus (f7-fa). channel current balance is essential in achieving the thermal advantage of multiphase operation. with good current balance, the power loss is equally dissipated over multiple devices and a greater area. voltage regulation the compensation network shown in figure 12 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (dac and offset) and droop current source, remote sense, and error amplifier. the sensed average current i droop is tied to fb internally and will develop voltage drop across the resistor between fb and v out for droop control. this current can be disconnected from the fb node by tying r fs_drp high to v cc for non-droop applications. the output of the error amplifier, v comp , is compared to the internal sawtooth waveforms to generate the pwm signals. the pwm signals control the timing of the intersil mosfet drivers and regulate the converter outp ut to the specified reference voltage. the ISL6381 does not have a unity gain amplifier in between the feedback path and error amplifier. for remote sensing, connect the microprocessor sensing pins to the non-inverting input, fb, via the feedback resistor (r fb ), and inverting input, rgnd, of the error amplifier. this configuration effectively removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point. vsen should connect to remote sensing?s positive rail as well for overvoltage protection. a digital-to-analog converter (dac) generates a reference voltage, which is programmable via svid bus or pmbus. the dac decodes the svid or pmbus set command into one of the discrete voltages shown in table 4 . in addition, the output voltage can be margined in 5mv step between -640mv and 635mv for vr12 mode, 10mv step between -1280mv and 1270mv for vr12.5 mode, as shown in table 4 , via svid set offset command (33h). for a finer than 5mv or 10mv offset, a large ratio resistor divider can be placed on the fb pin between the output and gnd for positive offset or vcc for negative offset, as in figure 13 . figure 9. desired load transient response waveforms i out v out figure 10. load transient response when r-c time constant is too small i out v out figure 11. load transient response when r-c time constant is too large i out v out figure 12. output voltage and load-line regulation i droop external circuit comp r c r fb fb - + v droop error v comp c c - + v out rgnd amplifier + + vid and offset ovp - + - + vsen ISL6381 dac figure 13. external programmable regulation - + dac = vid+offset fb e/a v cc v out - + dac = vid+offset fb e/a v out a. v out higher than dac b. v out lower than dac
ISL6381 20 fn8576.1 june 12, 2014 confidential submit document feedback table 4. vr12.5/vr12/imvp7 vid 8-bit binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv) 00000000 0 off off 0 0 00000001 1 0.250 0.500 5 10 00000010 2 0.255 0.510 10 20 00000011 3 0.260 0.520 15 30 00000100 4 0.265 0.530 20 40 00000101 5 0.270 0.540 25 50 00000110 6 0.275 0.550 30 60 00000111 7 0.280 0.560 35 70 00001000 8 0.285 0.570 40 80 00001001 9 0.290 0.580 45 90 00001010 a 0.295 0.590 50 100 00001011 b 0.300 0.600 55 110 00001100 c 0.305 0.610 60 120 00001101 d 0.310 0.620 65 130 00001110 e 0.315 0.630 70 140 00001111 f 0.320 0.640 75 150 00010000 10 0.325 0.650 80 160 00010001 11 0.330 0.660 85 170 00010010 12 0.335 0.670 90 180 00010011 13 0.340 0.680 95 190 00010100 14 0.345 0.690 100 200 00010101 15 0.350 0.700 105 210 00010110 16 0.355 0.710 110 220 00010111 17 0.360 0.720 115 230 00011000 18 0.365 0.730 120 240 00011001 19 0.370 0.740 125 250 00011010 1a 0.375 0.750 130 260 00011011 1b 0.380 0.760 135 270 00011100 1c 0.385 0.770 140 280 00011101 1d 0.390 0.780 145 290 00011110 1e 0.395 0.790 150 300 00011111 1f 0.400 0.800 155 310 00100000 20 0.405 0.810 160 320 00100001 21 0.410 0.820 165 330 00100010 22 0.415 0.830 170 340 00100011 23 0.420 0.840 175 350 00100100 24 0.425 0.850 180 360 00100101 25 0.430 0.860 185 370 00100110 26 0.435 0.870 190 380 00100111 27 0.440 0.880 195 390 00101000 28 0.445 0.890 200 400 00101001 29 0.450 0.900 205 410 00101010 2a 0.455 0.910 210 420 00101011 2b 0.460 0.920 215 430 00101100 2c 0.465 0.930 220 440 00101101 2d 0.470 0.940 225 450 00101110 2e 0.475 0.950 230 460 00101111 2f 0.480 0.960 235 470 00110000 30 0.485 0.970 240 480 00110001 31 0.490 0.980 245 490 00110010 32 0.495 0.990 250 500 00110011 33 0.500 1.000 255 510 00110100 34 0.505 1.010 260 520 00110101 35 0.510 1.020 265 530 00110110 36 0.515 1.030 270 540 00110111 37 0.520 1.040 275 550 00111000 38 0.525 1.050 280 560 00111001 39 0.530 1.060 285 570 00111010 3a 0.535 1.070 290 580 00111011 3b 0.540 1.080 295 590 00111100 3c 0.545 1.090 300 600 00111101 3d 0.550 1.100 305 610 00111110 3e 0.555 1.110 310 620 00111111 3f 0.560 1.120 315 630 01000000 40 0.565 1.130 320 640 01000001 41 0.570 1.140 325 650 01000010 42 0.575 1.150 330 660 01000011 43 0.580 1.160 335 670 01000100 44 0.585 1.170 340 680 01000101 45 0.590 1.180 345 690 01000110 46 0.595 1.190 350 700 01000111 47 0.600 1.200 355 710 01001000 48 0.605 1.210 360 720 01001001 49 0.610 1.220 365 730 01001010 4a 0.615 1.230 370 740 01001011 4b 0.620 1.240 375 750 table 4. vr12.5/vr12/imvp7 vid 8-bit (continued) binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv)
ISL6381 21 fn8576.1 june 12, 2014 confidential submit document feedback 01001100 4c 0.625 1.250 380 760 01001101 4d 0.630 1.260 385 770 01001110 4e 0.635 1.270 390 780 01001111 4f 0.640 1.280 395 790 01010000 50 0.645 1.290 400 800 01010001 51 0.650 1.300 405 810 01010010 52 0.655 1.310 410 820 01010011 53 0.660 1.320 415 830 01010100 54 0.665 1.330 420 840 01010101 55 0.670 1.340 425 850 01010110 56 0.675 1.350 430 860 01010111 57 0.680 1.360 435 870 01011000 58 0.685 1.370 440 880 01011001 59 0.690 1.380 445 890 01011010 5a 0.695 1.390 450 900 01011011 5b 0.700 1.400 455 910 01011100 5c 0.705 1.410 460 920 01011101 5d 0.710 1.420 465 930 01011110 5e 0.715 1.430 470 940 01011111 5f 0.720 1.440 475 950 01100000 60 0.725 1.450 480 960 01100001 61 0.730 1.460 485 970 01100010 62 0.735 1.470 490 980 01100011 63 0.740 1.480 495 990 01100100 64 0.745 1.490 500 1000 01100101 65 0.750 1.500 505 1010 01100110 66 0.755 1.510 510 1020 01100111 67 0.760 1.520 515 1030 01101000 68 0.765 1.530 520 1040 01101001 69 0.770 1.540 525 1050 01101010 6a 0.775 1.550 530 1060 01101011 6b 0.780 1.560 535 1070 01101100 6c 0.785 1.570 540 1080 01101101 6d 0.790 1.580 545 1090 01101110 6e 0.795 1.590 550 1100 01101111 6f 0.800 1.600 555 1110 01110000 70 0.805 1.610 560 1120 01110001 71 0.810 1.620 565 1130 table 4. vr12.5/vr12/imvp 7 vid 8-bit (continued) binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv) 01110010 72 0.815 1.630 570 1140 01110011 73 0.820 1.640 575 1150 01110100 74 0.825 1.650 580 1160 01110101 75 0.830 1.660 585 1170 01110110 76 0.835 1.670 590 1180 01110111 77 0.840 1.680 595 1190 01111000 78 0.845 1.690 600 1200 01111001 79 0.850 1.700 605 1210 01111010 7a 0.855 1.710 610 1220 01111011 7b 0.860 1.720 615 1230 01111100 7c 0.865 1.730 620 1240 01111101 7d 0.870 1.740 625 1250 01111110 7e 0.875 1.750 630 1260 01111111 7f 0.880 1.760 635 1270 10000000 80 0.885 1.770 -640 -1280 10000001 81 0.890 1.780 -635 -1270 10000010 82 0.895 1.790 -630 -1260 10000011 83 0.900 1.800 -625 -1250 10000100 84 0.905 1.810 -620 -1240 10000101 85 0.910 1.820 -615 -1230 10000110 86 0.915 1.830 -610 -1220 10000111 87 0.920 1.840 -605 -1210 10001000 88 0.925 1.850 -600 -1200 10001001 89 0.930 1.860 -595 -1190 10001010 8a 0.935 1.870 -590 -1180 10001011 8b 0.940 1.880 -585 -1170 10001100 8c 0.945 1.890 -580 -1160 10001101 8d 0.950 1.900 -575 -1150 10001110 8e 0.955 1.910 -570 -1140 10001111 8f 0.960 1.920 -565 -1130 10010000 90 0.965 1.930 -560 -1120 10010001 91 0.970 1.940 -555 -1110 10010010 92 0.975 1.950 -550 -1100 10010011 93 0.980 1.960 -545 -1090 10010100 94 0.985 1.970 -540 -1080 10010101 95 0.990 1.980 -535 -1070 10010110 96 0.995 1.990 -530 -1060 10010111 97 1.000 2.000 -525 -1050 table 4. vr12.5/vr12/imvp7 vid 8-bit (continued) binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv)
ISL6381 22 fn8576.1 june 12, 2014 confidential submit document feedback 10011000 98 1.005 2.010 -520 -1040 10011001 99 1.010 2.020 -515 -1030 10011010 9a 1.015 2.030 -510 -1020 10011011 9b 1.020 2.040 -505 -1010 10011100 9c 1.025 2.050 -500 -1000 10011101 9d 1.030 2.060 -495 -990 10011110 9e 1.035 2.070 -490 -980 10011111 9f 1.040 2.080 -485 -970 10100000 a0 1.045 2.090 -480 -960 10100001 a1 1.050 2.100 -475 -950 10100010 a2 1.055 2.110 -470 -940 10100011 a3 1.060 2.120 -465 -930 10100100 a4 1.065 2.130 -460 -920 10100101 a5 1.070 2.140 -455 -910 10100110 a6 1.075 2.150 -450 -900 10100111 a7 1.080 2.160 -445 -890 10101000 a8 1.085 2.170 -440 -880 10101001 a9 1.090 2.180 -435 -870 10101010 aa 1.095 2.190 -430 -860 10101011 ab 1.100 2.200 -425 -850 10101100 ac 1.105 2.210 -420 -840 10101101 ad 1.110 2.220 -415 -830 10101110 ae 1.115 2.230 -410 -820 10101111 af 1.120 2.240 -405 -810 10110000 b0 1.125 2.250 -400 -800 10110001 b1 1.130 2.260 -395 -790 10110010 b2 1.135 2.270 -390 -780 10110011 b3 1.140 2.280 -385 -770 10110100 b4 1.145 2.290 -380 -760 10110101 b5 1.150 2.300 -375 -750 10110110 b6 1.155 2.310 -370 -740 10110111 b7 1.160 2.320 -365 -730 10111000 b8 1.165 2.330 -360 -720 10111001 b9 1.170 2.340 -355 -710 10111010 ba 1.175 2.350 -350 -700 10111011 bb 1.180 2.360 -345 -690 10111100 bc 1.185 2.370 -340 -680 10111101 bd 1.190 2.380 -335 -670 table 4. vr12.5/vr12/imvp 7 vid 8-bit (continued) binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv) 10111110 be 1.195 2.390 -330 -660 10111111 bf 1.200 2.400 -325 -650 11000000 c0 1.205 2.410 -320 -640 11000001 c1 1.210 2.420 -315 -630 11000010 c2 1.215 2.430 -310 -620 11000011 c3 1.220 2.440 -305 -610 11000100 c4 1.225 2.450 -300 -600 11000101 c5 1.230 2.460 -295 -590 11000110 c6 1.235 2.470 -290 -580 11000111 c7 1.240 2.480 -285 -570 11001000 c8 1.245 2.490 -280 -560 11001001 c9 1.250 2.500 -275 -550 11001010 ca 1.255 2.510 -270 -540 11001011 cb 1.260 2.520 -265 -530 11001100 cc 1.265 2.530 -260 -520 11001101 cd 1.270 2.540 -255 -510 11001110 ce 1.275 2.550 -250 -500 11001111 cf 1.280 2.560 -245 -490 11010000 d0 1.285 2.570 -240 -480 11010001 d1 1.290 2.580 -235 -470 11010010 d2 1.295 2.590 -230 -460 11010011 d3 1.300 2.600 -225 -450 11010100 d4 1.305 2.610 -220 -440 11010101 d5 1.310 2.620 -215 -430 11010110 d6 1.315 2.630 -210 -420 11010111 d7 1.320 2.640 -205 -410 11011000 d8 1.325 2.650 -200 -400 11011001 d9 1.330 2.660 -195 -390 11011010 da 1.335 2.670 -190 -380 11011011 db 1.340 2.680 -185 -370 11011100 dc 1.345 2.690 -180 -360 11011101 dd 1.350 2.700 -175 -350 11011110 de 1.355 2.710 -170 -340 11011111 df 1.360 2.720 -165 -330 11100000 e0 1.365 2.730 -160 -320 11100001 e1 1.370 2.740 -155 -310 11100010 e2 1.375 2.750 -150 -300 11100011 e3 1.380 2.760 -145 -290 table 4. vr12.5/vr12/imvp7 vid 8-bit (continued) binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv)
ISL6381 23 fn8576.1 june 12, 2014 confidential submit document feedback load-line regulation some microprocessor manufacturers require a precisely controlled output resistance. th is dependence of the output voltage on load current is often termed ?droop? or ?load-line? regulation. by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction that works to achieve the load-line regulation required by these manufacturers. in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output volt age spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors selected. by positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without cr ossing the upper specification limit. as shown in figure 12 , a current proportional to the average current of all active channels, i avg , flows from fb through a load-line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage droop with a steady-state value defined, as shown in equation 11 : the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a fu nction of load current is derived by combining equation 11 with the appropriate sample current expression defined by the current sense method employed, as shown in equation 12 : where v ref is the reference voltage (dac), i load is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, and r fb is the feedback resistor, n is the active channel number, and r x is the dcr, or r sense depending on the sensing method. therefore, the equivalent loadline impedance, i.e. droop impedance, is equal to equation 13 : the major regulation error comes from the current sensing elements. to improve load-line re gulation accuracy, a tight dcr tolerance of inductor or a precis ion sensing resistor should be considered. in addition to adjusting r fb for the droop impedance, the droop impedance can be programmed as a percentage of r ll or disabled via pmbus (d3h, d4h). dynamic vid modern microprocessors need to make changes to their voltage as part of normal operation. they direct the core-voltage regulator to do this by making changes to the vid during regulator operation. the power management solution is required to monitor the dac and respond to on-the-fly vid changes in a controlled manner. supervising the safe output voltage transition within the dac range of the proc essor without discontinuity or disruption is a necessary function of the core-voltage regulator. three different kinds of dvid operation (fast, slow, decay) can be selected during dynamic vid (dvid) transition for vr, but during vr soft-start, the setvid slow rate is defaulted. the setvid rate is programmable via fs_dvid pin, as in table 5 , and smbus/pmbus/i 2 c, as in table 6 . in memory mode 11100100 e4 1.385 2.770 -140 -280 11100101 e5 1.390 2.780 -135 -270 11100110 e6 1.395 2.790 -130 -260 11100111 e7 1.400 2.800 -125 -250 11101000 e8 1.405 2.810 -120 -240 11101001 e9 1.410 2.820 -115 -230 11101010 ea 1.415 2.830 -110 -220 11101011 eb 1.420 2.840 -105 -210 11101100 ec 1.425 2.850 -100 -200 11101101 ed 1.430 2.860 -95 -190 11101110 ee 1.435 2.870 -90 -180 11101111 ef 1.440 2.880 -85 -170 11110000 f0 1.445 2.890 -80 -160 11110001 f1 1.450 2.900 -75 -150 11110010 f2 1.455 2.910 -70 -140 11110011 f3 1.460 2.920 -65 -130 11110100 f4 1.465 2.930 -60 -120 11110101 f5 1.470 2.940 -55 -110 11110110 f6 1.475 2.950 -50 -100 11110111 f7 1.480 2.960 -45 -90 11111000 f8 1.485 2.970 -40 -80 11111001 f9 1.490 2.980 -35 -70 11111010 fa 1.495 2.990 -30 -60 11111011 fb 1.500 3.000 -25 -50 11111100 fc 1.505 3.010 -20 -40 11111101 fd 1.510 3.020 -15 -30 11111110 fe 1.515 3.030 -10 -20 11111111 ff 1.520 3.040 -5 -10 table 4. vr12.5/vr12/imvp 7 vid 8-bit (continued) binary code hex code vr12 vid (v) vr12.5 vid (v) vr12 offset (mv) vr12.5 offset (mv) v droop i avg r ? fb = (eq. 11) v out v ref i load n ---------------- - r x r isen ----------------- -r fb ?? ?? ?? ? = (eq. 12) r ll r fb n ------------ r x r isen ----------------- - = (eq. 13)
ISL6381 24 fn8576.1 june 12, 2014 confidential submit document feedback (dvc_mem = v cc ), fast dvid rate is defaulted at 10mv/s, unless programmed by smbus/pmbus/i 2 c. setvid slow rate is always 1/4 of setvid fast rate. during dynamic vid transition an d vid step up, the overcurrent trip point increases by 140% to avoid falsely triggering ocp circuits, while the overvoltage trip point will follow dac+ovp (350mv or 175mv), which programmable via pmbus (d8[0]). if the dynamic vid occurs at psi1/2/3/decay (lower power state) asserted, the system should exit to psi0 (full power state) and complete the transition, and will not resume the lowe power state operation unless the low power mode command is asserted again. in addition to ramping down the output voltage with a controlled rate as previously described, vr can be programmed into decay mode via svid?s setdecay command. whenever the decay command is received, the vr will enter psi2 mode. the vr will be in single-phase operation. if the de register is selected to be ?enabled?, the vr will operate in diode emulation mode and drop to the target voltage at a deca y rate determined by the load impedance and output capacitive bank. the decay rate will be limited to 2.5mv/s rate setting. if the ?de? register is selected to be ?disabled?, then the vr will drop at 2.5mv/s rate setting. operation initialization prior to converter initialization, proper conditions must exist on the enable inputs and v cc . when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of operation, vr_rdy asserts logic high. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state (o r pulled to 40% of v cc ) to assure the drivers remain off. the following input conditions must be met before the ISL6381 is released from shutdown mode. 1. the bias voltage applied at v cc must reach the internal power-on reset (por) rising thre shold. once this threshold is reached, proper operation of all aspects of the ISL6381 is guaranteed. hysteresis between the rising and falling thresholds assure that once enabled, the ISL6381 will not inadvertently turn off unless the bias voltage drops substantially (see ?electrical specifications? table beginning on page 9 ). 2. the ISL6381 features an enable input (en_pwr_cfp) for power sequencing between the controller bias voltage and another voltage rail. the en able comparator holds the ISL6381 in shutdown until the voltage at en_pwr rises above 0.85v. the enable comparator has about 100mv of hysteresis to prevent bounce. it is import ant that the drivers reach their por level before the ISL6381 becomes enabled. the schematic in figure 14 demonstrates sequencing the ISL6381 with the isl66xx family of intersil mosfet drivers. 3. the voltage on tm_en_otp mu st be higher than 1.08v (typically) to enable the cont roller. this pin is typically connected to the output of vtt vr. however, since the tm_en_otp pin is also used for thermal monitoring, it will flag status_byte due to thermal alert prior to start-up, therefore, it needs to use clear_fault (03h) command to clear status_byte (78h). when all conditions previously mentioned are satisfied, the ISL6381 begins the soft-start and ramps the output voltage to the boot voltage set by hard-wired ?bt? register, e6h of pmbus, or first setvid command if boot voltage set to zero volts. after table 5. slew rate options via fs_dvid pin dvc_mem fs_dvid setvid fast (minimum rate) mv/s setvid slow (minimum rate) mv/s rc/ open v cc 10 2.5 gnd 20 5.0 v cc v cc 10 2.5 gnd 10 2.5 table 6. slew rate options via pmbus (f6h) pmbus f6h[2:0] fs_dvid (dvc_mem = open, rc) setvid fast (minimum rate) mv/s setvid slow (minimum rate) mv/s 0h v cc 10 2.5 1h gnd 20 5.0 2h n/a 14 3.5 3h n/a 17 4.3 4h n/a 26 6.5 5h n/a 32 8.0 6h n/a 40 10 7h n/a 53 13.3 figure 14. power sequencing using threshold-sensitive enable (en) function - + 0.85v external circuit ISL6381 en_pwr_cfp +12v por circuit 100k 9.09k enable comparator soft-start and fault logic tm_en_otp v cc + - 1.08v v cc 1k 6.8k ntc
ISL6381 25 fn8576.1 june 12, 2014 confidential submit document feedback remaining at the boot voltage for some time, the ISL6381 reads the vid code via svid bus. if the vid code is valid, ISL6381 will regulate the output to the final vid setting. if the vid code is ?off? code, ISL6381 will remain shutdown. soft-start the ISL6381 based vr has 4 periods during soft-start, as shown in figure 15 . after v cc , tm_en_otp and en_pwr reach their por/enable thresholds, the controller will have a fixed delay period t d1 . after this delay period, the vr will begin first soft-start ramp until the output voltage reaches v boot voltage at a fixed slew rate, one-quarter of setvid fast rate as in table 5 . then, the controller will regulate the vr voltage at v boot for another period t d3 until svid sends a new vid command. if the vid code is valid, ISL6381 will initiate the second soft-start ramp at a slew rate, set by setdvid fast or slow command in table 5 , until the voltage reaches the new vid voltage. the soft-start time is the sum of the 4 periods, as shown in equation 14 . the t d1 is a fixed delay with the typical value as 4.6ms, which becomes 0ms delay when a successful pmbus command is recognized during enable (e n_pwr_cfp or tm_en_otp) low shown in figure 38 . the t d3 is determined by the time to obtain a new valid vid voltage from svid bus. if the vid is valid before the output reaches the boot voltage, the output will turn around to respond to the new vid code. during t d2 and t d4 , the ISL6381 digitally controls the dac voltage change at 5mv per step . the soft-start ramp time t d2 and t d4 can be calculated based on equations 15 and 16 : for example, when the v boot is set at 1.1v and setvid rate is set at 10mv/s, the first soft-start ramp time t d2 will be around 440s and the second soft-start ramp time t d4 will be at maximum of 40s if an setvid command for 1.5v is received after t d3 . however, if v boot is set at 0v, the first setvid command is for 1.5v, then t d2 will be around 150s. note that the initial 0 to 250mv dac is typically at a slower rate to minimize the in-rush current, the response time could be dictated by the compensation network and the output filter. current sense output the current flowing out of the imon pin is equal to the sensed average current inside the ISL6381. in typical applications, a resistor is placed from the imon pin to gnd to generate a voltage, which is proportional to the load current and the resistor value, as shown in equation 17 : where v imon is the voltage at the imon pin, r imon is the resistor between the imon pin and gnd, i load is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, n is the active channel number, and r x is the dc resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method. the resistor from the imon pin to gnd should be chosen to ensure that the voltage at the imon pin is typically 2.5v at the maximum load current, typi cally corresponding to i ccmax register. the imon voltage is linearly digitized every 88s and stored in the iout register (15h). when the imon voltage reaches 2.5v or higher, the digitized iout will be ffh and the svalert# pin is pulled low to alarm the cpu. if the desired cpu maximum load current alert is not listed in table 11 (svid 21h register programmed by imax pin, not p mbus), a higher iccmax should be selected from table 11 , while the imon resistor should be scaled accordingly to make sure that it reaches 2.5v at the selected iccmax output load, as in the following. in intel cpu applications, the cpu itself scales the icc_max register (21h in table 14 ) to meet the cpu desired iccmax alert. a small capacitor can be placed between the imon pin and gnd to reduce the noise impact and provide averaging. the typical time constant is <200s for vr12.5 server core (i.e., 5.6nf for a 30k ? r imon ) and 1-2ms for desktop core applications. if this pin is not used, tie it to gnd. to deal with layout and design variation of different platforms, the ISL6381 is intentionally trimmed to negative range at no load, thus, an offset can easily be added to calibrate the digitized imon reading (15h in svid and 8ch in pmbus) whenever needed by pmbus (bfh) or the external pull-up resistor in figure 16 . hence, the slope on the imon pin is set by the equivalent impedance of r mon1 //r mon2 = ? r imon . figure 15. soft-start waveforms tm_en_otp t d3 t d4 vr_ready t d1 t d2 t ss t d1 t d2 t d3 t d4 +++ = (eq. 14) t d2 v boot setvid slow rate ---------------------------------------------------------- ? s ?? = (eq. 15) t d4 v vid v boot ? setvid rate --------------------------------------- - ? s ?? = (eq. 16) v imon r imon n -------------------- r x r isen ----------------- -i load = (eq. 17) (eq. 18) r imon 2.5v r isen r x -------------------------------- n i cc_max_21h -------------------------------------- = r mon2 v cc r imon v imon_offset_desired -------------------------------------------------------------------------- - = (eq. 19) r mon1 r imon2 r imon r imon2 r imon ? -------------------------------------------------- =
ISL6381 26 fn8576.1 june 12, 2014 confidential submit document feedback in addition, if the imon pin voltage is higher than 3.0v, overcurrent shutdown will be triggered, as described in ? overcurrent protection ? on page 26 . fault monitoring and protection the ISL6381 actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a micr oprocessor load. one common power-good indicator vr_rdy is provided for linking to external system monitors. the schematic in figure 17 outlines the interaction between the fault mo nitors and the vr_rdy signals. vr_ready signal the vr_rdy pin is an open-drain logic output that indicates when the soft-start period is complete and the output voltage is within the regulated range. the vr_rdy is pulled low during shutdown and releases high after a successf ul soft-start. the vr_rdy will be pulled low when an fault (ocp or ovp) condition is detected, or the controller is disabled by a reset from en_pwr_cfp, tm_en_otp, por, or vid off-code. if the multi_vr_config register is set to 01h, then the vr_ready line will stay high when receiving a 00h vid code after th e first soft-start. the defaulted multi_vr_config is 00h. overvoltage protection regardless of the vr being enabled or not, the ISL6381 overvoltage protection (ovp) circuit will be active after its por. the ovp thresholds are different unde r different operation conditions. prior to the end of the soft-start, the ovp threshold is 2.15v, which is also programmable via d8[2:1]. once the vr completes the soft- start, the ovp trip point will change to a tracking level of dac+ ovp (350mv or 175mv), which is programmable via pmbus (d8[0]). two actions are taken by the ISL6381 to protect the microprocessor load when an overvoltage condition occurs. at the inception of an overvolt age event, all pwm outputs are commanded low instantly. this causes the intersil drivers to turn on the lower mosfets and pull the output voltage below a level to avoid damaging the load. when the output voltage falls below the dac plus 100mv, pwm signals enter a high-impedance state. the intersil drivers respond to the high-impedance input by turning off both upper and lower mosfets. if the overvoltage condition reoccurs, ISL6381 will again command the lower mosfets to turn on. the ISL6381 will continue to protect the load in this fashion as long as the overvoltage condition occurs. once an overvoltage condition is detected, the vr ceases the normal pwm operation and pulls its vr_ready low until the ISL6381 is reset. cycling the voltage v cc below the por-falling threshold will reset the controller. cycling en_pwr or tm_en_otp will not reset the controller. in addition, the ISL6381 features open sensing protection to detect an open of the output voltage sensing as an ovp event, which suspends the controller oper ation. without this protection, the vr can regulate up to maxi mum duty cycle and damage the load and power trains when the output sensing is broken open. furthermore, since the regulation loop is sensed via the fb pin and the ovp is sensed via the vs en pin, they are independent paths to keep output within target and below ovp level, respectively. thus, the ISL6381 prot ects against a single point of failure. furthermore, since the regulation loop (fb pin) and the ovp sense (vsen) are separated paths, the ovp level can be programmed higher or lower than the target, as in figure 18 ; the ovp level however cannot be scaled too close to dac to ensure that the ovp is not triggered during transient response and start-up. overcurrent protection the ISL6381 has two levels of overcurrent protection. each phase is protected from a sustained over current condition by limiting its figure 16. imon no load offset calibration external circuit ISL6381 imon r mon 2 = #m r mon1 = #k svid digitized iout (15h) and v cc pmbus digitized iout (8ch) figure 17. vr_rdy and protection circuitry - + dac+ 0.350v vsen - + i avg ov oc soft-start, fault and control logic - + otp 0.95v ISL6381 imon vr_rdy - + oc 3.0v tm_en_otp i avg_ocp figure 18. external programmable ovp - + dac + 0.350v vsen ov vcc vout - + dac + 0.350v vsen ov vout a. increased ovp b. reduced ovp
ISL6381 27 fn8576.1 june 12, 2014 confidential submit document feedback peak current, while the combin ed phase currents are protected on an instantaneous basis. for the individual channel overcurrent protection, the ISL6381 continuously compares the sensed peak current (~50ns filter) signal of each channel with a reference current programmed by icl_spdup_k pin or pmbus (f4h, defaulted 125a). if one channel current exceeds the refere nce current, ISL6381 will pull the pwm signal of this channe l to low for the rest of the switching cycle. this pwm signal can be turned on next cycle if the sensed channel current is less than the reference current. the peak current limit of indivi dual channels will only use cycle-by-cycle current limiting an d will not trigger the converter to shutdown. in instantaneous protection mode, the ISL6381 utilizes the sensed average current i avg to detect an overcurrent condition. see ? current sensing ? on page 17 for more details on how the average current is measured. the average current is continually compared with a reference current ( i avg_ocp ,) programmed by pmbus (f4h, defaulted 100a), as shown in figure 17 . once the average current exceeds the reference current, a comparator triggers the converter to shutdown. in addition, the current out of the imon pin is equal to th e sensed average current i avg . with a resistor from imon to gnd, the voltage at imon will be proportional to the sensed averag e current and the resistor value. the ISL6381 continuously monitors the voltage at the imon pin. if the voltage at the imon pin is higher than 3.0v, a precision comparator triggers the overcurrent shutdown. since the internal current comparator has wider tolerance than the voltage comparator, the imon voltage comparator is the preferred one for ocp trip. therefore, the resistor between imon and gnd can be scaled such that the overcurrent protection threshold is tripping lower than i avg_ocp . for example, the overcurrent threshold for the sensed average current i avg can be set to 95a by using a 31.6k ? resistor from imon to gnd. thus, the internal overcurrent comparator (say defaulted 100a) might only be triggered at its lower corner. however, imon ocp trip should not be too far away from cycle-by-cycle reference current, which is used for cycle-by-cycle protection and inductor saturation. at the beginning of overcurrent shutdown, the controller places all pwm signals in a high-impedance stat e, commanding the intersil mosfet driver ics to turn off both upper and lower mosfets. the system remains in th is state a period of 8ms. if the controller is still enabled at th e end of this wait period, it will attempt a soft-start. if the fault remains, the trip-retry cycles will continue indefinitely (as shown in figure 19 ) until either controller is disabled or the fault is cleared. note: that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard during this kind of operation. thermal monitoring (vr_hot#) and protection the vr_hot# indicates the temper ature status of the voltage regulator. vr_hot# is an open-d rain output, and an external pull-up resistor is required. this signal is valid only after the controller is enabled. the vr_hot# signal can be used to inform the system that the temperature of the voltage regulator is too high and the cpu should reduce its power consumption. the vr_hot# signal may be tied to the cpu?s proc_hot signal. the thermal monitoring function block diagram is shown in figure 20 . one ntc resistor should be placed close to the respective power stage of the voltage regulator vr to sense the operational temperature, and pu ll-up resistors are needed to form the voltage dividers for the tm pin. as the temperature of the power stage increases, the resi stance of the ntc will reduce, resulting in the reduced voltage at the tm pin. figure 21 shows the tm voltage over the temperature for a typical design with a recommended 6.8k ntc (p/n: nths0805n02n6801 from vishay, b = 3477) and 1k resistor r tm . it is recommended to use those resistors for the accurate temperature compensation since the internal thermal digita l code is developed based upon these two components. if a different value is used, the temperature coefficient must be close to 3477 and r tm must be scaled accordingly. for instance, ntc = 10k (b = 3477), then r tm should be 10k /6.8k *1k = 1.47k . there is a comparator with hysteresis to compare the tm pin voltage to the threshold set by the tmax register for vr_hot# signal. with tmax is set at +100c, the vr_hot# signal is pulled to gnd when the tm pin voltage is lower than 39.12% of the v cc voltage, and is open (pulled high through tm) when the tm voltage increase to above 40.98% of the v cc voltage. the comparator trip point will be programmable by tmax values. 0a 0v 2ms/div output current figure 19. overcurrent behavior in hiccup mode f sw = 500khz output voltage figure 20. block diagram of thermal monitoring function vcc vr_hot# o c r tm tm - + r ntc1 thermal trip point lookup table (+85c to +120c) tmax ISL6381 ntc beta ~ 3477
ISL6381 28 fn8576.1 june 12, 2014 confidential submit document feedback figure 22 shows the operation of those signals. based on the ntc temperature characteristics and the desired threshold of the vr_hot# signal, the pull-up resistor r tm of tm pin is given by equation 20 : r ntc(t2) is the ntc resistance at the vr_hot# threshold temperature t2. the vr_hot# is deasserted at temperature t1, as shown in table 7 . the ntc directly senses the temperature of the pcb and not the exact temperature of the hottest component on the board due to airflow and varied thermal impedance. therefore, the user should select a lower tmax number, depending upon the mismatch between ntc and the hottest components, than such component to guarantee a safe operation. in addition, as the temperature increase, the voltage on the tm pin drops. the controller is disabled when the tm pin voltage drops below 0.95 (typically) and be comes active again when it is above 1.08v (typically). note: when the tm_en_otp pin is used for enable toggle input, it will flag status_byte (78h) due to thermal alert prior to start-up, therefore, it needs to use clear_fault (03h) command to clear status_byte (78h). temperature compensation the ISL6381 supports inductor dcr sensing, or resistive sensing techniques. the inductor dcr has a positive temperature coefficient, which is about +0. 385%/c. since the voltage across the inductor is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr. in order to obtain the correct current information, there should be a way to correct the temperature impact on the current sense component. the ISL6381 provides two methods: integrated temperature compensation and external temperature compensation. integrated temperature compensation the ISL6381 utilizes the voltage at the tm pin and ?tcomp? register to compensate the temperature impact on the sensed current. the block diagram of this function is shown in figure 23 . when the ntc is placed close to the current sense component (inductor), the temperature of th e ntc will track the temperature of the current sense component. therefore, the tm voltage can be utilized to obtain the temperature of the current sense component. since the ntc could pick up noise from the phase table 7. vr_hot# typical trip point and hysteresis tmax (c) vr_hot# low (c, t2, %v cc ) vr_hot# open (c, t1, %v cc ) hysteresis (c) +85 83.1; 48.94% 80.3; 51.04% 2.7 +90 88.6; 45.52% 85.9; 47.56% 2.7 +95 94.3; 42.26% 91.4; 44.20% 2.9 +100 100.0; 39.12% 97.1; 40.98% 2.9 +105 106.1; 36.14% 103.0; 37.92% 3.1 +110 109.1; 33.32% 106.1; 35.00% 3.0 +115 115.5; 30.68% 112.3; 32.24% 3.2 figure 21. the ratio of tm voltage to ntc temperature with recommended parts 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 temperature ( o c) v tm /v cc (%) figure 22. vr_hot# signal (tmax = +100c) vs tm voltage tm vr_hot# 40.98%*vcc 39.12%*vcc temperature t1 t2 r tm 1.557xr ntc t2 ?? = (eq. 20) +120 118.7; 28.24% 115.5; 29.7% 3.2 table 7. vr_hot# typical trip point and hysteresis (continued) tmax (c) vr_hot# low (c, t2, %v cc ) vr_hot# open (c, t1, %v cc ) hysteresis (c) figure 23. block diagram of integrated temperature compensation o c r tm r nt c tm tcomp non-linea r a /d 4-bit a /d droop and overcurrent protection i 1 i 2 i 3 i 4 k i d/ a channel current sense i sen4 i sen3 i sen2 i sen1 v cc place ntc close to channel 1 ISL6381
ISL6381 29 fn8576.1 june 12, 2014 confidential submit document feedback node, a 0.1f ceramic decoupling capacitor is recommended on the tm pin in close proximity to the controller. based on the v cc voltage, the ISL6381 converts the tm pin voltage to a 6-bit tm digital sign al for temperature for accurate temperature compensation, the ratio of the tm voltage to the ntc temperature of the practical de sign should be similar to that in figure 21 . since the ntc attaches to the pcb, but not directly to the current sensing component, it inherits high thermal impedance between the ntc and the current sensing element. the ?tcomp? register values can be utilized to correct the temperature difference between ntc and the current sense component. as shown in figure 24 , the ntc should be placed in proximity to the psi channel and the output rail; do not place it close to the mosfet side, which generates much more heat. the ISL6381 multiplexes the ?tcomp? value with the tm digital signal to obtain the adjustment gain to compensate the temperature impact on the se nsed channel current. the compensated channel current signal is used for droop and overcurrent protection functions. when a different ntc type or different voltage divider is used for the tm function, the tcomp voltage can also be used to compensate for the difference between the recommended tm voltage curve in figure 21 and that of the ac tual design. if the same type ntc ( ? = 3477) but different value is used, the pull-up resistor needs to be scaled, as shown in equation 21 : design procedure 1. properly choose the voltage divider for the tm pin to match the tm voltage vs temperature curve with the recommended curve in figure 21 . 2. run the actual board under the full load and the desired cooling condition. 3. after the board reaches the thermal steady state, record the temperature (t csc ) of the current sense component (inductor or mosfet) and the voltage at tm and vcc pins. 4. use equation 22 to calculate the resistance of the ntc, and find out the corresponding ntc temperature t ntc from the ntc datasheet or using equation 23 , where b is equal to 3477 for recommended ntc. 5. in intersil design worksheet, choose a number close to the result in equation 24 in the ?tcomp? cell to calculate the needed resistor network for the register ?tcomp? pin. note: for worksheet, please contact intersil application support at www.intersil.com/design/ . 6. run the actual board under full load again with the proper resistors connected to the ?tcomp? pin. 7. record the output voltage as v1 immediately after the output voltage is stable with the full load. record the output voltage as v2 after the vr reaches the thermal steady state. 8. if the output voltage increases over 2mv as the temperature increases, i.e. v2 - v1 > 2mv, reduce ?tcomp? value; if the output voltage decreases over 2mv as the temperature increases, i.e. v1 - v2 > 2m v, increase ?tcomp? values. external temperature compensation when the ?off? code of tcomp is selected, then the internal current source is not thermally co mpensated, i.e, the integrated temperature compensation function is disabled. however, one external temperature compensation network, shown in figure 25 , can be used to cancel the temperature impact on the droop (i.e; load-line). the sensed current will flow out of the fb pin and develop a droop voltage across the resistor equivalent (r fb ) between the fb pin and vout sensing node. if r fb resistance reduces as the table 8. ?tcomp? values tcomp (c) tcomp (c) -2.5 +18.9 +2.5 +24.3 +7 +29.7 +13 off figure 24. recommended placement of ntc vout phase1 power stage output inductor ntc r tm 1k ? r ntc_new ? 6.8k ? ----------------------------------------------- - = (eq. 21) r ntc t ntc ?? v tm xr tm v cc v ? tm ----------------------------- - = (eq. 22) t ntc ? rtm r ntc t ntc ?? ------------------------------------ ?? ?? ? 298.15 ----------------- - + ln ------------------------------------------------------------------------ - 273.15 ? = (eq. 23) t comp t csc t ntc ? = (eq. 24) figure 25. external temperature compensation for load-line fb vout o c idroop comp ISL6381
ISL6381 30 fn8576.1 june 12, 2014 confidential submit document feedback temperature increases, the temperature impact on the droop can be compensated. an ntc resistor can be placed close to the power stage and used to form r fb . due to the nonlinear temperature characteristics of the ntc, a resi stor network is needed to make the equivalent resistance between the fb pin and vout sensing node inversely proportion al to the temperature. this external temperature co mpensation network can only compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6381. therefore, this network cannot compensate for the temperature impact on the overcurrent protection function. in addition, the ntc could pick up phase switching noise and easily inject into the loop. this method is typically not recommended. furthermore, the ntc can be placed with l/dcr matching network to thermally compensate the sensed current, or with imon network to thermally compensate the imon voltage (typically need to set internal ov ercurrent trip to be higher than imon ocp trip), as shown in figures 26 and 27 , respectively. these methods are typically applicable for non-droop applications. hard-wired registers (patented) to set registers using lowest pin-count package and with lowest overall cost, intersil has developed a high resolution adc using a patented technique with simple 1%, 100ppm/k or better temperature coefficient resistor divider, as shown in figure 28 . the same type of resistors are pr eferred so, that it has similar change over-temperature. in additi on, the divider is compared to the internal divider off vcc and gnd nodes and therefore must refer to vcc and gnd pins, not through any rc decoupling network. as an example, tables 12 and 13 show the r up and r dw values of each pin for a specific system design; data for corresponding registers can be read out via svid?s get(reg) command. in addition, some tie-high and tie-low options are available for easy programming (save resistor dividers) and can also be used to validate the vr operation during in-circuit test (ict). for instance, when the system boot voltage is required at 0, the imadr_btrm pin can be tied to gnd or vcc, prior to enable, to get a known boot voltage to check vr operation with ict. resistor register calculator is available, please contact intersil application support at www.intersil.com/design/ . figure 26. ntc with l/dcr matching network for thermal compensation isen- o c phase isen+ ISL6381 figure 27. ntc with imon network for thermal compensation imon o c ISL6381 figure 28. simplified resistor divider adc external circuit ISL6381 r up r dw v cc adc register table
ISL6381 31 fn8576.1 june 12, 2014 confidential submit document feedback table 9. system parameter description register pin name data register code (svid) data register code (pmbus) imadr_btrm 0c dc tmx_drp_de_tc 0d dd vdband_pmadr_vrsel 0e de icl_spdupc_k of b0 table 10. system parameter description code name description range addr svid v core : 0 with pmbus address of 80, 82, 84, 86 v mem : 2, 4, 6, 8 pmaddr pmbus e0, e2, e4, e6, e8, ea, ec, ee, 88, 8a, 8c, 8e, c8, ca, cc, ce bt boot voltages (dvc_mem = rc or open) 0, 1.65, 1.7, 1.75v boot voltages (dvc_mem = v cc ) 0, 1.2, 1.35, 1.5 fdvid setvid fast slew rate 10, 20mv/s via pin or 10 to 53mvs via pmbus command (f6h) de diode emulation option enable, or disable tmax maximum operating temperature +85c to +120c (5c/step) imax i ccmax of platforms (1a/step via pmbus) limited by pin in table 11 ; or 0-255a via pmbus npsi number of operational phases in psi1 state 1 or 2-phase tcomp mismatching temperature compensation between sensing element and ntc off, -2.5c to +29.7c ramp upramp amplitude 1.2v and 1.5v via pin 0.75, 1.0, 1.2, 1.5v via pmbus command (fd) icl cycle-by-cycle over current limit 70a to 125a spdupc sensitivity of speed up control 2pf to 16pf (2pf/step, no 14pf selection), and original k comp voltage clamp control threshold original, 0.25, 0.5, 0.75 vdband comp ripple voltage band 12.5v to 100mv (12.5mv/step)
ISL6381 32 fn8576.1 june 12, 2014 confidential submit document feedback table 11. imax value at different phase count by ?imax? pin 4-phase (a) 3-phase (a) 2-phase (a) 1-phase (a) 80 60 40 10 90 70 46 15 100 75 52 20 120 52 60 25 140 95 65 30 165 100 70 35 175 112 75 40 190 135 85 45 table 12. desogn exaple (dvc_mem = rc, 4-phase) reg r up r dw data 0c imax addrs bt ramp 215 0/80 1.7v 1.2v 665 k ? 187 k ? c2h 0d tmax droop de tcomp +100c enabled enabled +13c 17.4 k ? 23.2 k ? 14h +100c 0e vdband pmaddr vrsel d-band0 n/a n/a open 10 k ? 0h 0f icl spdupc k 100% 4pf 0.25 open 10 k ? 0h table 13. design example (dvc_mem = v cc , 2-phase) reg r up r dw data 0c imax addrs bt ramp 60 2 127v 1.2v 200 k ? 69.8 k ? 64h 0d tmax droop de tcomp +100c enabled enabled +13c 17.4 k ? 23.2 k ? 14h 0e vdband pmaddr vrsel d-band0 e0 vr12.5 open 10 k ? 0h e0 vr12 open 499 k ? e0h 0f icl spdupc k 100% 4pf 0.25 97.6 k ? 53.6 k ? 49h
ISL6381 33 fn8576.1 june 12, 2014 confidential submit document feedback high frequency compensation connect a resistor of the same or slightly higher (~ 150%) value as the feedback impedance (r fb ) to the vr output to compensate the level-shifted output voltage during high frequency load transient events. connecting more than 3x of r fb to this pin virtually disables this feature. when the droop disabled, an additional 500k from this pin to vcc, as shown in figure 30 , is needed to ensure proper operation when the integrator capacitance from comp to fb is too low (typically les than ~68pf). dynamic vid compensation (dvc) during a vid transition, the resultin g change in voltage on the fb pin and the comp pin causes an ac current to flow through the error amplifier compensation components from the fb to the comp pin. this current then flows through the feedback resistor, r fb , and can cause the output voltage to overshoot or undershoot at the end of the vid transition. in order to ensure the smooth transition of the output voltage during a vid change , a vid-on-the-fly compensation network is required. this network is composed of a resistor and capacitor in series, r dvc and c dvc , between the dvc and the fb pin. this vid-on-the-fly compensation network works by sourcing ac current into the fb node to offset the effects of the ac current flowing from the fb to the comp pin during a vid transition. to create this compensation current, the controllers set the voltage on the dvc pin to be 4/3 of the voltage on the dac. since the error amplifier forces the voltage on the fb pin and the dac to be equal, the resulting voltage across the series r c between dvc and fb is equal to the dac voltage. the r c compensation components, r dvc and c dvc , can then be selected to create the desired amount of compensation current. . the amount of compensation curre nt required is dependant on the modulator gain of the system, k1, and the error amplifier r-c components, r c and c c , that are in series between the fb and comp pins. use equations 25 , 26 , and 27 to calculate the r-c component values, r dvc and c dvc , for the vid-on-the-fly compensation network. for these equations: v in is the input voltage for the power train; v ramp is the oscillator ramp amplitude as in equation 3 ; and r c and c c are the error amplifier r-c components between the fb and comp pins. during dvid transitions, extra current builds up in the output capacitors due to the c*dv/dt. the current is sensed by the controller and fed across the feedback resistor creating extra droop (if enabled) and causing th e output voltage not properly tracking the dac voltage. placing a series r-c to ground from the fb pin can sink this extra dvid induced current. when the output voltage overshoots during dvid, the rdvc-cdvc network can be used to compensate the movement of the error-amplifier compensation network. when the output voltage is lagging from dac (or svalert#) or having a rough-off prior to the final settling of dvid, the r-c network can be used to compensate for the extra droop current generated by the c*dv/dt. sometimes, both networks can work together to achieve the best result. in such ca ses, both networks need to be fine tuned in the board level for optimized performance. in memory mode, the dvc pin is not available for use. catastrophic fault protection a catastrophic failure is a failure that will result in an exothermic event if the power source is not removed. a predominate catastrophic failure is a high-side fet shorting, which can cause figure 29. high frequency compensation network e/a hfcomp v cc r hfcomp v out v dac ~ 500k hf(s) fb - + droop disabled e/a hfcomp r hfcomp v out v dac hf(s) fb - + droop enabled figure 30. dynamic vid compensation network ISL6381 internal circuit error amplifier c dvc r dvc - + x1.333 c c r c dvc fb comp r fbs v out i dvc i c i dvc = i c v dac c r i rc +i droop_actual i rc k1 v in v ramp -------------------- = (eq. 25) r dvc ar c ? = (eq. 26) a k1 3k11 ? ?? ? ----------------------------- = c dvc c c a ------- - = (eq. 27) c c out r ll ? r fb ------------------------------- = (eq. 28) r c out r ll ? c ------------------------------- r fb == (eq. 29) figure 31. bidirectional en_pwr_cfp vin r up r dw1 en_pwr_cfp cfp cfp vcc reset en_pwr r dw2 ISL6381
ISL6381 34 fn8576.1 june 12, 2014 confidential submit document feedback either an output overvoltage or an input overcurrent event. when the ISL6381 detects either event, an internal switch is turned on to pull the en_pwr_cfp pin to vcc, as an indication of a component failure in the regulator?s power train. as shown in figure 31 , a cfp fault signal can be generated by using a resistor divider on this pin. to be able to apply the signal to the ps_on# switch of an atx power supply or a simply external switch (2n7002), the cfp fault signal should be lower than 0.8v at maximum input voltage, vin(max) and higher than 3v at lowest normal operational vcc (4.5v) wh en the input voltage (vin) is removed. given such conditions , the equivalent (in parallel) impedance of the upper leg (r up ) and lower leg (r dw =r dw1 +r dw1 ) should be higher than 1k ? . for instance, if we select the total lower leg impedance (r dw ) as 9.39k ? , then the r up is calculated as in equation 31 , 100k ? for an maximum por of 10.72v, the lower leg impedance is then calculated by 2.74k ? and 6.65k ? , as in equations 32 and 33 , respectively. prior to an exothermic event, th e fault signal (cfp) should be used on the platform to remove the power source either by firing a shunting scr to blow a fuse or by turning off the ac power supply. input current sensing the input current sensing uses intersil patented technique to overcome the high common-mode input requirement challenge. an r-c network with thermal co mpensation across the inductor (lin) extracts the dcr voltage, as shown in figure 32 , while the c might need to be split into 2; one close the lin and one close to the controller. the input inductor can be used for current sensing and has the benefit of isolating no ise from the rest of the board. however, when there are insufficient bulk capacitors on the power-stage side, a resonant tank can be formed by input ceramic capacitors and the inductor, yielding oscillation or audio noise during audio frequency rang e of heavy load transient. in addition, since z ntc network steals portion of sensed current from r 1 , input current reading will have offset. in many cases, a narrow input-rail pcb trace (but wide enough to carry dc current) is sufficient to serve as the isolation path. thus, the input current sensing can simply be realized with an dedicated power resistor, as shown in figure 33 . the full scale of input current sensing is 10 a, read 1fh with read_iin(89h), via pmbus, while the input overcurrent trip point is at 15 a. a design worksheet to select these components is available for use. please contac t intersil application support at www.intersil.com/design/ . when not used, connect isenin+ to v in and a resistor divider with a ratio of 1/3 on the isenin pin (say 499k ) in between isenin pins and then 1.5m from isenin- to ground (see figure 34 ). r dw r dw1 r dw2 + = (eq. 30) r up vin por max ? ?? 0.92v ? 0.92v ------------------------------------------------------------------- r dw ? = (eq. 31) r dw1 vin max ?? 0.8v ---------------------------- r up r dw + ?? ? = (eq. 32) r dw2 r dw r dw1 ? = (eq. 33) figure 32. input dcr-sensing configuration ntc vin_hs_mosfet vin r 1 r 2 dcr isenin- (pin 1) isenin+ (pin 2) rsn rpn z ntc place ntc close to lin lin 10nf 1.8f 0.3m ? 2k ? 215 ? 10.2k ? 50nh 165 ? 402 0.1f place close to the controller vin_hs_mosfet vin r 2 r senin isenin- (pin 1) isenin+ (pin 2) 10nf c r 1 l r_senin 0.1f 43.2 ? 562 ? 0.3m ? 1nh 0.1f place close to the controller figure 33. input r-sensing configuration vin_hs_mosfet isenin- (pin 1) isenin+ (pin 2) 0.1f place close to the controller 499k ? 1.5m ? figure 34. disable pin and iin configuration
ISL6381 35 fn8576.1 june 12, 2014 confidential submit document feedback auto-phase shedding in addition to low power mode (psi1/2/3/decay) operation, the ISL6381 also incorporates auto -phase shedding feature to improve light to medium load range. the phase current dropping threshold is programmable with the iauto pin. the efficiency-optimized current trip point (i1) from 1-phase to 2- phase operation is approximated with equation 34 , which is k times larger than the efficiency-optimized current trip step (di = i3 - i2) in between from 2-phase to 3-phase (i2) and from 3-phase to 4-phase (i3). the optimized-efficiency current trip point difference between phases remain constant i1/k. where p qg is the per-phase gate charge loss, p core is the inductor core loss, p qoss is the sum of high-side and low-side mosfets? output charge loss. equation 37 helps approximate the impedance on the auto pin, while the trip point hysteresis should be selected accordingly in table 14 . typically, the higher the inductor ripple current, the higher percentage of hysteresis and k it requires. following is an easy way to estimate r auto value: 1. disable auto mode via pmbus (e4 = 1h) or by tying auto pin gnd and set vr at desired output level via pmbus or svid bus. 2. disable apa level via pmbus (f0 = 0h). 3. obtain efficiency curve for 1 to 4-phase by programming pmbus command, d0. 4. determine i1 from the above test result. 5. short auto pin to ground with a current meter to measure the imon current (i imon_optimized_1_phase ) when vr is at i1 load. 6. calculate r auto as in equation 36 . 7. solder down both r auto and c auto (start with 56nf) and then enable auto mode by removing the short from auto pin. 8. take efficiency curve and compare it with 1 to 4-phase efficiency curves. 9. tweak both r auto and c auto as needed for optimal efficiency performance at targeted operating input and output voltage as well as airflow. 10. obtain efficiency curve for couple boards and tweak both r auto and c auto to recenter overall efficiency of these boards. the auto-phase shedding feature ca n be disabled when this pin is tied high or shorted to gnd. although the auto-phase shedding is disabled, the low power mode operation still can be programmed via svid bus. in addition, the smbus, pmbus, or i 2 c gives flexibility to program number of operating phases. the minimum of auto-phase shedding is defaulted by npsi in psi1 mode (si1 = 1-phase and si2 = 2-phase), as in table 3 , and can also be programmed by the bus command code d1h, as in table 20 . the phase dropping sequence is summarized in table 15 . table 14. auto threshold and nspi selection options c auto (nf) k hysteresis npsi auto pin shorted to vcc auto off si2 0.82 1.5 12.5% si2 2.7 1.75 25% si2 8.2 1.75 25% si1 22 1.25 25% si1 56 1.5 12.5% si1 auto pin shorted to gnd auto off si1 i1 2p qg p core p coss ++ ?? ? esr in dr on l ds f sw ? ++ ? --------------------------------------------------------------------------------- - ? (eq. 34) r on dr ds on ?? _up ? 1d ? ?? r ds on ?? _low ? dcr ++ = i imon_optimized_1_phase 64 d ? cr i1 ? n max r ? set ------------------------------------ ? (eq. 35) r auto 1.2v i imon_optimized_1_phase -------------------------------------------------------------------------- - = (eq. 36) r auto 1.2v n max r ? set ? 64 d ? cr i1 ? ----------------------------------------------------- - ? (eq. 37) i n ?? i1 1 1 k --- - n1 ? ?? ? + ?? ?? ? ? (eq. 38) figure 35. simplified auto-phase shedding circuit external circuit ISL6381 r si2 r auto v cc phase shedding c auto auto current threshold selection load (a) figure 36. efficiency vs phase number e f f i c i e n c y ( % ) i1 i2 i3 i4 i5 94 93 92 91 90 89 88 87 86 85 0 20 60 80 100 120 140 160 180 40
ISL6381 36 fn8576.1 june 12, 2014 confidential submit document feedback to ensure dropped phases have sufficient energy to turn on the high-side mosfet and sustain inst ant load apply after vr staying in light load condition for a long time (hours to days), a boot-refresh circuit turns on lo w-side mosfet of each dropped phase to refresh the boot capacito r at a rate of slightly above 20khz. the boot-fresh circuit is automatically turned off to boot efficiency when dac drops to 0.60v. to guarantee system reliability an d robust operation during auto mode operation, there are two actions: 1. the vr adds dropped phases back when the operational phase(s) carry too much current and triggers the thermal apa level, programmable via pmbus (ebh); 2. the vr immediately adds dropped phases back when the vr voltage drops and triggers the apa level, programmable via pmbus (f0h). svid operation the device is compliant with intel vr12.5/vr12/imvp7 svid protocol. to ensure proper cpu op eration, refer to this document for svid bus design and layout guidelines; each platform requires different pull-up impedance on the svid bus, while impedance matching and spacing among da ta, clk, and alert# signals must be followed. common mist akes are insufficient spacing among signals and improper pull-up impedance. a simple operational instruction of svid bus with intel vtt tool is documented in ?vr12.5 design and validation? in table 26 . table 15. phase dropping sequence n pwm# tied to v cc (vcore) pwm# tied to v cc (memory) phase sequence psi# = psi0 4 x_mem= v cc 4-2-3-1 3pwm4 pwm4 3-2-1 2pwm3 pwm3 2 table 16. svid supported registers index name description access default 00h vendor id intel assigned vr vendor id r 12h 01h product id intersil unique product id r 61h 02h product revision r01h 05h protocol id vr12 = 01h vr12.5 = 02h r?vrsel? pin 06h capability vr capability register 0h = not supported; 1h = supported bit0 = iout (15h) = 1 bit1 = vout (16h) = 1 bit2 = pout (18h) = 1 bit3 = i input (19h) = 1 bit4 = v input (1ah) = 1 bit5 = p input (1bh) = 1 bit6 = temperature (17h) = 0 bit7 = 1 (1 if 15h is formatted ffh = icc_max; 0 if 15h is formatted 1a per_lsb) isenin in use = bfh isenin not used = 97h (not support vin, iin, pin 1/3 divider on these pins) rbfh or 97h 10h status_1 at end of soft-start r 01h 11h status_2 r 00h 12h tempzone r 00h 15h iout digital reading of imon r 00h 1ch status_last read a copy of the status_2 data that was last read with getreg (11h) command r 00h 21h icc_max also programmable via smbus/pmbus/i 2 c r ?im? and pwmx pin 22h temp_max r?tmx? pin 24h sr_fast programmable via ?fdvid? and ?mem? pins: 0ah = ?>10mv/s? 14h = ?>20mv/s? or pmbus f6[3:0]: 10mv/s to 53mv/s r 0ah or 14h by pin; or 0ah to 35h by pmbus
ISL6381 37 fn8576.1 june 12, 2014 confidential submit document feedback the supported svid/pmbus address are in pairs: 0/80, 0/82, 0/84 and 0/86 when ?vr? = v core ; 2, 4, 6 and 8 when ?vr? = memory. a resistor register calculator is available for use to set the svid address. smbus, pmbus, and i 2 c operation the ISL6381 features smbus, pmbus, and i 2 c with programmable address via hard-wired registers as in figure 28 , while smbus/pmbus includes packet erro r check (pec) to ensure data properly transmitted. in addition, the output voltage, droop slope, enable, operating phas e number, overvoltage setpoint, and the priority of svid and smbus/pmbus/i 2 c can be written and read via this bus, as summarized in table 20 . input, output, fault, and temperature telemetries can be read as summarized in table 21 . for proper operation, users shou ld follow the smbus, pmbus, and i 2 c protocol, as shown figure 39 . note that stop (p) bit is not allowed before the repeated start condition when ?reading? contents of register, as shown in figure 39 (#3). the supported smbus/pmbus/i 2 c addresses are in 8-bit format (including write and read bit): 80-8e, e0 to ee, and c8-ce. the least significant bit of the 8-bit a ddress is for write (0h) and read (1h). for reference purpose, the 7-bit format addresses are also summarized in table 18 . there are a series set of read and write commands as summarized in tables 20 and 21 , respectively. the smbus/pmbus/i 2 c allows to program the registers as in table 10 , except for svid and smbus/pmbus/i 2 c addresses, 11ms after vcc above por and prior to enable pins (en_pwr_cfp) high. the bus can also program default contents during this period. if all enable pins are high before the 9ms expires or no bus command is received during enable pins low, the register values are defaulted by the hard-wired 4-pin resister setting. if no pmbus write comm and is successfully received during enable high or low, the register values can be reprogrammed by the using different resistor dividers during enable low; otherwise, other than the svid and pmbus addresses, all other settings can be reprogrammed by the respective pmbus commands, as in table 20 . a resistor register calculator is available for use to set the svid address. please contact intersil appl ication support at www.intersil.com/design/ . the 88h-8eh are two-byte word re ads with pec (if applicable), while 78h, f2h, and other write command codes are one-byte word reads with pec (if applicable). 25h sr_slow programmable via ?fdvid? and ?mem? pins: 02h = ?>2.5mv/s? 05h = ?>5mv/s? or pmbus f6[3:0]: 1/4 of sr_fast r 02h or 05h by pin; or 02h to 0dh by pmbus 26h vboot programmable via ?bt? pin; or via pmbus e6h[7:0] prior to enable high rw ?bt? pin or pmbus e6h 30h vout_max maximum allowable dac rw ffh 31h vid setting rw vboot 32h power state rw 00h 33h offset rw 00h 34h multi_vr_config set vr_ready state when setvid 0v after first boot rw 00h 35h setregadr rw 00h note: capability (06h) depends upon isenin co nfiguration. boot voltage, icc_max, tmax, and slew rate (sr_fast and sr_slow) can be programmed via pmbus/smbus/i 2 c prior vr enable or during operation. there is no nvm in th e ISL6381, therefore, the conf iguration must be stored in bios or embedded pmbus controller to take effect for next power up. alternatively, the ISL6381 can be biased by standby power t o keep the configuration active. table 16. svid supported registers (continued) index name description access default table 17. svid/pmbus address (hex) ?vr? = vcore ?vr? = memory svid pmbus svid pmbus 0802programmable via pmaddr register pin 0824 0846 0868 e/f for all call
ISL6381 38 fn8576.1 june 12, 2014 confidential submit document feedback table 18. smbus/pmbus/i 2 c 8-bit and 7-bit format address (hex) 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 80/81 40 e0/e1 70 c8/c9 64 82/83 41 e2/e3 71 ca/cb 65 84/85 42 e4/e5 72 cc/cd 66 86/87 43 e6/e7 73 ce/cf 67 88/89 44 e8/e9 74 8a/8b 45 ea/eb 75 8c/8d 46 ec/ed 76 8e/8f 47 ee/ef 77 table 19. example of 4 cpus address partitioning 4 cores (v core ) 16 memories smbus/ pmbus/i 2 csvidsmbus/ pmbus/i 2 csvid 80/81 0 88/89 2 82/83 0 8a/8b 4 84/85 0 8c/8d 6 86/87 0 8e/8f 8 e0/e1 2 e2/e3 4 e4/e5 6 e6/e7 8 e8/e9 2 ea/eb 4 ec/ed 6 ee/ef 8 c8/c9 2 ca/cb 4 cc/cd 6 ce/cf 8 note: the ISL6381 alone can support 4 cores and 16 memories. figure 37. simplified smbus/pmbus/i 2 c initialization timing diagram wh en no bus write command received 5v v cc enable 9ms 2ms v cc por time out reader done reader re-loaded 4.6 ms indefinitely reader re-loaded 4.6ms d0 to f3 command resistor divider to reset 0c- 0e user can change v out program configuration d0 to f3 command no successful bus send command (bt, max, npsi, de, etc.) use previous programmed configuration for startup figure 38. simplified smbus/pmbus/i 2 c initialization timing diagram when bus write command 5v vcc enable 9ms 2ms vcc por time out reader done indefinitely d0 to f3 command d0 to f3 command d0 to f3 command dc to df command program configuration (bt, tmax, npsi, de, etc.) vout program configuration (bt, tmax, npsi, de, etc.) program configuration (bt, tmax, npsi, de, etc.) use previous programmed configuration for startup and operation
ISL6381 39 fn8576.1 june 12, 2014 confidential submit document feedback figure 39. smbus/pmbus/i 2 c protocol s slave address_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a 1 p s slave address_0 1 7 + 1 command code 1 8 a 1 a pec 8 1 a 1 p optional 9 bits for smbus/pmbus 1. send byte protocol 2. write byte/word protocol s slave address_0 1 7 + 1 command code 1 8 a 1 8 a 1 8 a 1 8 a 1 n 1 p 3. read byte/word protocol rs slave address_1 1 7 + 1 example command: 03h clear faults example command: dah set_vid (one word, high data byte and ack are not used) not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c example command: 8b read_v out (two words, read voltage of the selected rail). s: start condition a: acknowledge (?0?) n: not acknowledge (?1?) rs: repeated start condition p: stop condition pec: packet error checking r: read (?1?) w: write (?0?) 5. alert response address (ara, 0001_1001, 25h) for smbus and pmbus, not used for i 2 c s alert addr_1 1 7 + 1 1 7+1 a 1 a 8 1 a 1 p optional 9 bits for smbus/pmbus not used in i 2 c 1 a data byte pec 8 1 8 a 1 a 4. group command protocol - no more than one command can be sent to the same address rs slave addr2_0 1 7 + 1 1 a s slave addr1_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a low data byte high data byte pec 8 1 8 a 1 8 a 1 a 1 p rs slave addr3_0 1 7 + 1 optional 9 bits for smbus/pmbus 1 a not used in i 2 c note that all writable commands are read with one byte word protocol. not used for one byte word read not used for one byte word slave_address_1 pec low data byte high data byte pec command code 8 1 a command code 8 1 a (this will clear all of the bits in status byte for the selected rail) acknowledge or data from slave, ISL6381 controller stop (p) bit is not allowed before the repeated start condition when ?reading? contents of a register. a
ISL6381 40 fn8576.1 june 12, 2014 confidential submit document feedback table 20. smbus, pmbus, and i 2 c write and read registers command code access default command name description d0h[2:0] r/w n phase operate_phase_number 0h = 7h = n max ; 1h=1 phase; 2h=2 phases; 3h=3 phases; 4h=4 phases. n max set by pwmx hard wired; for instance if pwm4 = vcc, n max = 3 phases. d0 should not be written until 50ms after soft-start and rewritten after dvid. when auto (rc to gnd) function is enabled, d0h cannot use to program phase number but it reports the operating phase number. d1h[1:0] r/w n psi min_phase_number minimum number of auto phase shedding: 0h = 1-phase; 1h = 2-phase; 2h = 3-phase; 3h = 4-phase. d2h[1:0] r/w 00h auto_blank time between subsequent phase drops: 0h = 4.6ms; 1h = 2.3ms; 2h = 1.2ms; 3h = 0.6ms d3h[2:0] r/w 00h droop_trim 0h = 100%, 1h = 75%, 2h = 50%, 3h = 25%, 4h = 5% d4h[0] r/w ?drp? pin droop_en 0h = droop disabled; 1h = droop enabled; default by pin. d5h[1:0] r/w 00h freq_limiter maximum pwm sust ained frequency under repetitive load: 0h = 2 fsw; 1h = 3/2 fsw; 2h = 3h = infinity frequency limiter is not available for new speedup (b2 0h) d6h[1:0] r/w 00h lock_svid set svid and smbus/pmbus/i 2 c priority (see table 22 for details) d7h[0] r/w 01h enable 0h = disabled; 1h = enabled d8h[2:0] r/w ?vrsel? pin and 2.15v set_ovp ovp during operation (after end of soft start, defaulted by vrsel pin): d8[0]: 0h = 175mv, 1h = 350mv; ovp = vid+ d8[0] default: 0h for vr12 mode, 1h for vr12.5 mode; prior to end of soft-start (fixed ovp, default 2h): d8[2:1]: 0h = 3.350v, 1h = 2.65v; 2h = 2.150v; 3h = 1.85v; d9h[0] r/w ?de? pin diode_emulation# 0h = enabled; 1h = disabled dah[7:0] r/w ?bt? pin set_vid svid bus vid code (see table 4 ) dbh[7:0] r/w 00h set_offset svid bus offset code (see table 4 ) dc-deh[7:0] b0h[7:0] r ?im?,?tmx? ?vdband? ?icl? pins config registers reference to resistor reader. dc maps to config_0c, dd maps to config_0d, de maps to config_0e; b0 maps config_0f. df[4:0] r/w 0h protection_disable protection disable [0, 0, 0, iph_limit, ocp_v, ocp_i, iin_ocp, ovp] iph_limit = phase cycle-by-cycle current limiting; ocp_v = output ocp trip at imon pin; ocp_i = outp ut ocp trip at 100a; iin_ocp = input overcurrent trip; ovp = output overvoltage. e1[1:0] r/w ?auto? pin auto_k programmable auto mode k factor: 0h = 1.25; 1h = 1.5; 2h = 1.75; 3h = 1.0; default by auto pin. e2[1:0] r/w ?auto? pin auto_hys programmable auto mode hysteresis factor: 0h = 50%; 1h = 25%; 2h = 16.6%; 3h = 12.5%; default by auto pin. e4[0] r/w ?auto? pin auto_disable disable auto mode: 0h = enabled; 1h = disabled e5[1:0] r/w 00h auto_i1 programming i1 in auto mode: 0h = 100%; 1h = 80%; 2h = 90%; 3h = 110%. e6[7:0] r/w ?bt? pin b00t_voltage program vboot (26h) in svid : vr12.5: 0, 0.5v to 3.04v; vr12: 0, 0.25 to 1.52v. see table 4 . e7[0] r/w ?npsi? pin npsi ps1 phase co unt: 0h = 1-phase; 1h = 2-phase e8[2:0] r/w ?tmx? pin tmax program temp_max (22h) in svid : 0h = 100c; 1h = +105c; 2h = +110c; 3h = +115c; 4h = +120c; 5h = +85c; 6h = +90c; 7h = +95c e9[2:0] r/w ?tc? pin tcomp 0h = off; 1h = -2.5c; 2h = +2.5c; 3h = +7c; 4h = +13c; 5h =+18.9c; 6h = +24.3c; 7h = +29.7 c. ea[7:0] r/w ?im? and pwmx pins imax program icc_max (21h) in svid : 0 to 255a, 1a/step; 0h: ffh = 0a: 255a eb[1:0] r/w 00h thermal_apa thermal trigger apa level to add phases in auto mode: 0h = 75%; 1h = 82%; 2h = 91%; 3h = 100% of tmax
ISL6381 41 fn8576.1 june 12, 2014 confidential submit document feedback ec[0] r/w 00h pos_ll_en positive load-line: 0h = disabled; 1h = enabled ed[1:0] r/w 00h pos_ll positive load-line range: 0h = 4mv, 1h = 8mv; 2h = 16mv, 3h = 32mv at imon full scale of 3v. 0mv when imon = 0v. ee[0] r/w 00h freq_dither frequency dithering: 0h = off; 1h = on, -12.5k , 0, 12.5khz ef[1:0] r/w 00h cfp 0h = 100%, 1h = 110%, 2h = 120%; 3h = 130% f0h[2:0] r/w 02h apa_trigger_level apa trigge r level to add phases in auto mode: 0h = disable; 1h = 10mv; 2h = 20mv; 3h = 30mv; 4h = 40mv; 5h = 50mv; 6h = 60mv; 7h = 70mv f1h[1:0] r/w 03h apa_time_constant 0h = tsw; 1h = tsw/2; 2h = tsw/4; 3h = tsw/8. f3h[0] r/w 01h boot_refresh_enable 0h = disa bled; 1h = enabled. boot refresh ci rcuits is automatically turned off when dac is lower than 0.605v. f4[1:0] r/w 00h ocp_trim ocp trim level for average ocp and cycle-by-cycle limiting: 0h = 1.0, 1h = 1.1, 2h = 1.2; 3h = 1.4 of imon f5h[5:0] r/w 0fh freq_trim programmable range -187.5 khz (0h) to 600khz (3f) with ~12.5khz/step above based frequency (set by fs pin). see table 24 . f6h[3:0] r/w 0h or 1h by ?fdvid? and ?mem? pins fdvid program setvid_fast (24h) in svid : 0h = 10mv/s; 1h = 20mv/s; 2h = 14mv/s; 3h = 17mv/s; 4h = 26mv/s; 5h = 32mv/s; 6h = 40mv/s; 7h = 53mv/s f7h[2:0] f8h[2:0] f9h[2:0] fah[2:0] r/w 4h f7 = bal_trim_phase1 f8 = bal_trim_phase2 f9 = bal_trim_phase3 fa = bal_trim_phase4 0h = -12% of full scale 1h = -9% of full scale 2h = -6% of full scale 3h = -3% of full scale 4h = no offset 5h = +3% of full scale 6h = +6% of full scale 7h = +9% of full scale fd[1:0] r/w 2h or 3h by ?rm? pin vramp 0h = 0.75v; 1h = 1v; 2h = 1.2v; 3h = 1.5v bf[4:0] r/w trim imon_trim 0h = 0.00a ...............................10h = -0.25a 1h = 0.25a................................11h = -0.50a 2h = 0.50a................................12h = -0.75a 3h = 0.75a................................13h = -1.00a 4h = 1.00a................................14h = -1.25a 5h = 1.25a................................15h = -1.50a 6h = 1.50a................................16h = -1.75a 7h = 1.75a................................17h = -2.00a 8h = 2.00a................................18h = -2.25a 9h = 2.25a................................19h = -2.50a ah = 2.50a................................1ah = -2.75a bh = 2.75a................................1bh = -3.00a ch = 3.00a................................1ch = -3.25a dh = 3.25a................................1dh = -3.50a eh = 3.50a.................................1eh = -3.75a fh = 3.75a.................................1fh = -4.00a b1[2:0] r/w ?icl? pin cycle_limiting cycle-by-cycle limiting, on top of f4h (data not valid until enable): 0h = 125%; 1h = 110%; 2h = 100%; 3h = 95%; 4h = 90% 5h = 85%; 6h = 80; 7h = 70% b2[2:0] r/w ?spdupc? pin speedup_ctrl speed up ca pacitance control (data not valid until enable): 0h = original; 1h = 2pf;2h = 4pf; 3h = 6pf; 4h = 8pf; 5h = 10pf; 6h = 12pf;7h = 16pf; the hi gher the capacitance, the faster the speed, but could lead to ps1/2 to ps0 transition oscillation. use caution . b3[1:0] r/w ?k? pin compbt_k comp voltage clamp to fire pwm pulses (data not valid until enable): 0h = original; 1h = 0.25; 2h = 0.5; 3h = 0.75. table 20. smbus, pmbus, and i 2 c write and read registers (continued) command code access default command name description
ISL6381 42 fn8576.1 june 12, 2014 confidential submit document feedback b4[2:0] r/w ?vdband? pin vdband d-b and comp ripple speed up control (data not valid until enable): 0h = 12.5mv; 1h = 25mv; 2h = 37.5mv; 3h = 50mv; 4h = 62.5mv; 5h = 75mv; 6h = 87.5mv; 7h = 100mv; 03h w clear_faults clear ?latched? fault registers in 78h for selected rail ara r alert_response_addre ss 8-bit address: 0001_1001, 25h; 7-bit address: 0c note: when the controller is reset by the en able pins (tm_en_otp or en_pwr), the prog rammed registers will be stored as long the re is still have power on vcc. svid?s boot voltage, icc_max, tmax, and slew rate (sr_fast and sr_slow) can be programmed via pmbus/smbus/i 2 c prior vr enable or during operation. there is no nvm in the ISL6381, therefore, th e configuration must be stored in bios or embedded pmbus control ler to take effect for next power-up. alternatively, the ISL6381 can be biased by standby power to keep the configuration active. table 20. smbus, pmbus, and i 2 c write and read registers (continued) command code access default command name description table 21. smbus, pmbus, and i 2 c telemetries code word length (byte) command name description typical resolution 88h two read_vin input voltage (25.5v = ff) 8-bit, 100mv 89h two read_iin input current (1fh = 10a) 5-bit, iin_full/31 (~1a) 8bh two read_vout output voltage (up to 3.04v) (see figure 41 ) 10-bit, 5mv 8ch two read_iout output current (iccmax = 2.5v imon) 8-bit, ~1a 8dh two read_temperature_1 tm temperature (see table 23 ) 8-bit, ~1c* 96h two read_pout output power ~2w (at 2v,l 1a lsb) 97h two read_pin input power ~12w (at 12v, 1a lsb) 78h one status_byte (read with one byte word + pec) fault reporting; bit5 = overvoltage; bit4 = overcurrent, ?? i max ; bit2= over-temperature, ?? t max ; bit1 = communication error. when tm_en_otp is used as an enable, bit2 will flag ot (= 1), clear_faults (03h) command must be sent to clear the fault after vr start-up. [0, 0, ov, oc, 0, ot, cml, 0] f2h one cpu_power_state vr operating power stage: 0h = psi0; 1h = psi1; 2h = psi2 (or decay); 3h = psi3 note: the 88h-8eh are two bytes word, while all others are one byte word. table 22. lock_svid d6h svid smbus, pmbus or i 2 c final dac targeted applications setvid setps (1/2/3) and setdecay set offset setvid set offset 00h yes yes yes not not sv_vid + sv_offset not overclocking 01h yes yes ack only not yes sv_vid + pm_offset not overclocking 02h yes ack only ack only not yes sv_vid + pm_offset overclocking 03h ack only ack only ack only yes yes pm_vid + pm_offset overclocking note: the ISL6381 controller is designed to be such that all sv id commands are always acknowledged as if the smbus, pmbus or i 2 c does not exist. to avoid the conflict between smbus/pmbus/i 2 c and svid bus during operation, the user should ex ecute this command prior to enable (tm_en_otp and en_pwr_cfp) high or during the boot period. when operating in 01h option, smbus/pmbus/i 2 c?s offset should only adjust slightly higher or lower (say 20mv) than svid offset for margining purpos e or pcb loss compensation so that cpu wi ll not draw significantly more power in ps i1/2/3/decay mode. to program full range of pm_offset for overclocking applications, the user should select 02h or 03h options. 03h option gives u sers full control of the output voltage (vid+offset) via smbus/pmbus/ i2 c, commonly used in overclocking applications. prio r to a successful written pmbus vid or offset, the controller will continue executing svid vid or offset command.
ISL6381 43 fn8576.1 june 12, 2014 confidential submit document feedback table 23. typical temperature (8dh and 8eh) temp. (0c) v tm(s) of vcc (%) code (hex) temp. (0c) v tm(s) of vcc (%) code (hex) 0 95.0 f2 71 58.9 96 1 94.8 f1 72 58.2 94 2 94.6f1 7357.592 3 94.4 f0 74 56.7 90 4 94.1 f0 75 56.0 8e 5 93.9 ef 76 55.3 8d 6 93.6 ee 77 54.6 8b 7 93.4 ee 78 53.9 89 8 93.1 ed 79 53.2 87 9 92.8 ec 80 52.4 85 10 92.6 ec 81 51.7 83 11 92.3 eb 82 51.0 82 12 92.0 ea 83 50.3 80 13 91.6 e9 84 49.6 7e 14 91.3 e8 85 48.9 7c 15 91.0 e7 86 48.2 7b 16 90.7 e7 87 47.6 79 17 90.3 e6 88 46.9 77 18 89.9 e5 89 46.2 75 19 89.6 e4 90 45.5 74 20 89.2 e3 91 44.9 72 21 88.8 e2 92 44.2 70 22 88.4 e1 93 43.5 6f 23 88.0 e0 94 42.9 6d 24 87.6 df 95 42.3 6b 25 87.2 de 96 41.6 6a 26 86.7 dd 97 41.0 68 27 86.3 dc 98 40.4 66 28 85.8 da 99 39.7 65 29 85.4 d9 100 39.1 63 30 84.9 d8 101 38.5 62 31 84.4 d7 102 37.9 60 32 83.9 d6 103 37.3 5f 33 83.4 d4 104 36.7 5d 34 82.9 d3 105 36.1 5c 35 82.4 d2 106 35.5 5a 36 81.9 d0 107 35.0 59 37 81.3 cf 108 34.4 57 38 80.8 cd 109 33.9 56 39 80.2 cc 110 33.3 54 40 79.7 cb 111 32.8 53 41 79.1 c9 112 32.2 52 42 78.5 c8 113 31.7 50 43 77.9 c6 114 31.2 4f 44 77.3 c5 115 30.7 4e 45 76.7 c3 116 30.2 4d 46 76.1 c2 117 29.7 4b 47 75.5 c0 118 29.2 4a 48 74.8 be 119 28.7 49 49 74.2 bd 120 28.2 48 50 73.5 bb 121 27.8 46 51 72.9 b9 122 27.3 45 52 72.2 b8 123 26.9 44 53 71.6 b6 124 26.4 43 54 70.9 b4 125 26.0 42 55 70.2 b3 126 25.5 41 56 69.5 b1 127 25.1 40 57 68.8 af 128 24.7 3e 58 68.2 ad 129 24.3 3d 59 67.5 ac 130 23.9 3c 60 66.8 aa 131 23.5 3b 61 66.1 a8 132 23.1 3a 62 65.4 a6 133 22.7 39 63 64.6 a4 134 22.3 38 64 63.9 a3 135 21.9 37 65 63.2 a1 136 21.6 36 66 62.5 9f 137 21.2 36 67 61.8 9d 138 20.8 35 68 61.1 9b 139 20.5 34 69 60.3 99 140 20.1 33 70 59.6 98 table 23. typical temperature (8dh and 8eh) (continued) temp. (0c) v tm(s) of vcc (%) code (hex) temp. (0c) v tm(s) of vcc (%) code (hex)
ISL6381 44 fn8576.1 june 12, 2014 confidential submit document feedback figure 40 shows a typical measurement of programmed switching frequency via pmbus (f5h). for lower than 400khz, the step changes to ~10khz/step. the output voltage reads out wi th a 10-bit adc with a typical resolution of 5mv. for example, a 1cch = 460dec = 460*5mv/1000 = 2.3v. figure 41 shows the vout_adc accuracy at various vcc voltage. for a better accuracy, a higher range vcc, but below 5.5v, is preferred. general design guide this design guide is intended to provide a high-level explanation of the steps necessary to create a multiphase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs, which include schematics, bills of materials, and example board layouts for common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases. this dete rmination depends heavily upon the cost analysis, which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power supply circuitry. generally sp eaking, the most economical solutions are those in which each phase handles between 15a and 25a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat dissipating surfaces accuracy. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct; the swit ching frequency; the capability of the mosfets to dissipate heat; and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for heat dissipated in the lower mosfet is simple, since virtually all of the heat loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). table 24. frequency trim table f5h freq (khz) f5h freq (khz) f5h freq (khz) f5h freq (khz) 0 -187.5 10 12.5 20 212.5 30 412.5 1 -175.0 11 25.0 21 225.0 31 425.0 2 -162.0 12 37.5 22 237.5 32 437.5 3 -150.0 13 50.0 23 250.0 33 450.0 4 -137.5 14 62.5 24 262.5 34 462.5 5 -125.0 15 75.0 25 275.0 35 475.0 6 -112.5 16 87.5 26 287.5 36 487.5 7 -100.0 17 100.0 27 300.0 37 500.0 8 -87.5 18 112.5 28 312.5 38 512.5 9 -75.0 19 125.0 29 325.0 39 525.0 a -62.5 1a 137.5 2a 337.5 3a 537.5 b -50.0 1b 150.0 2b 350.0 3b 550.0 c -37.5 1c 162.5 2c 362.5 3c 562.5 d -25.0 1d 175.0 2d 375.0 3d 575.0 e -12.5 1e 187.5 2e 387.5 3e 587.5 f 0.0 1f 200.0 2f 400.0 3f 600.0 figure 40. programmable frequency accuracy figure 41. v out _adc vs v cc at room temperature
ISL6381 45 fn8576.1 june 12, 2014 confidential submit document feedback in equation 39 , i m is the maximum continuous output current; i pp is the peak-to-peak inductor current (see equation 1 on page 14 ); d is the duty cycle (v out /v in ); and l is the per-channel inductance. an additional term can be ad ded to the lower mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f sw ; and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower mosfet conduction interval respectively. finally, the power loss of output capacitance of the lower mosfet is approximated in equation 41 : where c oss_low is the output capacitance of lower mosfet at the test voltage of v ds_low . depending on the amount of ringing, the actual power dissipation will be slightly higher than this. thus, the total maximum power dissipated in each lower mosfet is approximated by the summation of plow,1, plow,2 and plow,3. upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substant ially higher portion of the upper mosfet losses are dependent on switching frequency, the power calculation is more complex. uppe r mosfet losses can be divided into separate components involving the upper mosfet switching times; the lower mosfet body-diode reverse-recovery charge, q rr ; and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the induct or current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 42 , the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 43 , the approximate power loss is p up,2 . a third component involves the lower mosfet?s reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower mosfet?s body diode can draw all of q rr , it is conducted through the upper mosfet across v in . the power dissipated as a result is p up,3 and is approximated in equation 44 : the resistive part of the upper mosfet?s is given in equation 45 as p up,4 . equation 46 accounts for some power loss due to the drain-source parasitic inductance (l ds , including pcb parasitic inductance) of the upper mosfets, although it is not the exact: finally, the power loss of output capacitance of the upper mosfet is approximated in equation 47 : where c oss_up is the output capacitance of lower mosfet at test voltage of v ds_up . depending on the amount of ringing, the actual power dissipation will be slightly higher than this. the total power dissipated by the upper mosfet at full load can now be approximated as the su mmation of the results from equations 42 to 47 . since the power equations depend on mosfet parameters, choosing the correct mosfets can be an iterative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. current sensing resistor the resistors connected to the isen+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. select values for these resistors by using equation 48 : where r isen is the sense resistor connected to the isen+ pin, n is the active channel number, r x is the resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method, and i ocp is the desired overcurrent trip point. typically, i ocp can be chosen to be 1.2 times the maximum load current of the specific application. with integrated temperature co mpensation, the sensed current signal is independent of the operational temperature of the power stage, i.e. the temperature effect on the current sense element r x is cancelled by the integrated temperature compensation function. r x in equation 48 should be the resistance of the current sense element at the room temperature. when the integrated temperature compensation function is disabled by selecting ?off? tcom p code, the sensed current will be dependent on the operational temperature of the power stage, since the dc resistance of the current sense element may p low 1 ? r ds on ?? i m n ----- - ?? ?? ?? 2 i pp 2 12 --------- - +1d ? ?? ? = (eq. 39) p low 2 ? v don ?? f sw i m n ----- - i pp 2 -------- - + ?? ?? t d1 i m n ----- - i pp 2 -------- - ? ?? ?? ?? t d2 + = (eq. 40) p low 3 , 2 3 -- - v in 1.5 c oss_low v ds_low f sw ?? ? ? ? (eq. 41) p up 1 , v in i m n ----- - i pp 2 -------- - + ?? ?? t 1 2 ---- ?? ?? ?? f sw ? (eq. 42) p up 2 , v in i m n ----- - i pp 2 -------- - ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f sw ? (eq. 43) p up 3 , v in q rr f sw = (eq. 44) (eq. 45) p up 4 , r ds on ?? i m n ----- - ?? ?? ?? 2 i pp 2 12 --------- - +d ? ? p up 5 , l ds i m n ----- - i pp 2 -------- - + ?? ?? ?? 2 ? (eq. 46) p up 6 , 2 3 -- - v in 1.5 c oss_up v ds_up f sw ?? ? ? ? (eq. 47) r isen r x 100 10 6 ? ? -------------------------- - i ocp n ------------- - = (eq. 48)
ISL6381 46 fn8576.1 june 12, 2014 confidential submit document feedback be changed according to the op erational temperature. the r x in equation 48 should be the maximum dc resistance of the current sense element at the all operational temperature. in certain circumstances, espe cially for a design with an unsymmetrical layout, it may be necessary to adjust the value of one or more isen resistors for vr. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channe ls run cooler than the average, choose new, larger values of r isen for the affected phases (see the section entitled ? current sensing ? on page 17 ). choose r isen,2 in proportion to the desired increase in temperature rise in order to cause proportionally more current to flow in the cooler phase, as shown in equation 49 : in equation 49 , make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the ambient temperature. since all channels? r isen are integrated and set by one rset, a resistor ( ? r isen ) should be in series with the cooler channel?s isen+ pin to raise this phase current. while a single adjustment according to equation 49 is usually sufficient, it may occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. load-line regulation resistor the load-line regulation resistor is labelled r fb in figure 12 . its value depends on the desired loadline requirement of the application. the desired loadline can be calculated using equation 50 : where i fl is the full load current of the specific application, and vr droop is the desired voltage droop un der the full load condition. based on the desired loadline r ll , the loadline regulation resistor can be calculated using equation 51 : where n is the active channel number, r isen is the sense resistor connected to the isen+ pin, and r x is the resistance of the current sense element, either the dcr of the inductor or r sen depending on the sensing method. if one or more of the current sense resistors are adjusted for thermal balance (as in equation 49 ), the load-line regulation resistor should be se lected based on the average value of the current sensing resistors, as given in equation 52 : where r isen(n) is the current sensing resistor connected to the n th isen+ pin. output filter design the output inductors and the outp ut capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient energy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. the output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the outp ut capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in ch oosing the output capacitors are the maximum size of the load step, ? i; the load-current slew rate, di/dt; and the maximum allowable output voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and es l (equivalent series inductance). at the beginning of the load transi ent, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the vo ltage drop across the esl. as the load current increases, the volt age drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initia lly deviates by an amount, as shown in equation 53 : the filter capacitor must have sufficiently low esl and esr so that dv < dv max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see ? interleaving ? on page 14 and equation 2 ), a voltage develops acro ss the bulk-capacitor esr equal to i c,pp (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v pp(max) , determines the lower limit on the inductance, as shown in equation 54 . since the capacitors are supplying a decreasing portion of the load current while the regulator re covers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper li mit on inductance. r isen,2 r isen ? t 2 ? t 1 ---------- = (eq. 49) ? r isen r isen,2 r isen ? = r ll v droop i fl ------------------------ - = (eq. 50) r fb nr ? isen r ? ll r x ----------------------------------------- - = (eq. 51) r fb r ll r x ---------- r isen n ?? n ? = (eq. 52) ? vesl ?? di dt ---- - esr ??? i + ? (eq. 53) l esr v out k rcm ? f sw v in v ? pp max ?? ? ----------------------------------------------------------- ? ? (eq. 54)
ISL6381 47 fn8576.1 june 12, 2014 confidential submit document feedback equation 55 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output voltage deviation than the leading edge. equation 56 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lo wer of the two results. in each equation, l is the per channel in ductance, c is the total output capacitance, and n is the number of active channels. switching frequency selection there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper mosfet loss calculation. thes e effects are outlined in ? mosfet s ? on page 44 , and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output voltage ripple as outlined in ? output filter design ? on page 46 . choose the lowest switching frequency that allows the regulato r to meet the transient-response and output voltage ripple requirements. input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets, which is related to duty cycle and the number of active phases. the input rms current can be calculated with equation 57 . for a 2-phase design, use figure 42 to determine the input capacitor rms current requirement given the duty cycle, maximum sustained output current (i o ), and the ratio of the per-phase peak-to-peak inductor current (i l,pp ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors sh ould also be at least 1.25 times greater than the maximum input voltage. figures 28 and 30 provide the same input rms current information for 3 and 4-phase designs respectively. use the same approach to selecting the bulk capacitor type and number as previously described. l 2ncv ? out ?? ? i ?? 2 ----------------------------------------- ? v max ? iesr ? ? ? (eq. 55) l 1.25 nc ?? ? i ?? 2 ---------------------------- - ? v max ? i esr ? ? v in v out ? ?? ?? ? (eq. 56) i in rms ? k in cm ? 2 io 2 ? k ramp cm ? 2 i lo pp ? 2 ? + = (eq. 57) k in cm ? nd ? m ? 1 + ?? mnd ? ? ?? ? n 2 --------------------------------------------------------------------------- - = (eq. 58) k ramp cm ? m 2 nd ? m ? 1 + ?? 3 m1 ? ?? 2 mnd ? ? ?? 3 + 12n 2 d 2 ------------------------------------------------------------------------------------------------------------------ = (eq. 59) 0.3 0.1 0 0.2 input-capacitor current (i rms /i o ) figure 42. normalized input capacitor rms current vs duty cycle for 2-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o duty cycle (v out /v in ) figure 43. normalized input capacitor rms current vs duty cycle for 3-phase converter 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l,pp = 0 i l,pp = 0.25 i o i l,pp = 0.5 i o i l,pp = 0.75 i o input-capacitor current (i rms/ i o ) figure 44. normalized input capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) 0.3 0.1 0 0.2 i l,pp = 0 i l,pp = 0.25 i o i l,pp = 0.5 i o i l,pp = 0.75 i o
ISL6381 48 fn8576.1 june 12, 2014 confidential submit document feedback low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. the result from the high current slew rates produced by the upper mosfets turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize no ise suppression. multiphase rms improvement figure 45 is provided as a reference to demonstrate the dramatic reductions in input-capacitor rms current upon the implementation of the multiphase topology. for example, compare the input rms current requirements of a 2-phase converter versus that of a single phase. assume both converters have a duty cycle of 0.25, maximum sustained output current of 40a, and a ratio of i l,pp to i o of 0.5. the single phase converter would require 17.3a rms current capacity while the 2-phase converter would only require 10.9a rms . the advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach. layout and design considerations the following layout and design strategies are intended to minimize the noise coupling, the impact of board parasitic impedances on converter performance and to optimize the heat dissipating capabilities of the printed-circuit board. this section highlights some important practices, which should be followed during the layout process. a layout checklist in excel format is available for use. pin noise sensitivity, design and layout consideration table 25 shows the noise sensitivity of each pin and their design and layout consideration. all pins and external components should not be across switching no des and should be placed in general proximity to the controller. figure 45. normalized input capacitor rms current vs duty cycle for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) input-capacitor current (i rms/ i o ) 0.6 0.2 0 0.4 i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o table 25. pin design and/ or layout consideration pin name noise sensitive description isenin- yes connect to the input supply side of the input inductor or resistor pin with l/dcr or esl/r matching network in close proximity to the controller. place ntc in the close proximity to the input inductor for thermal compensation. a local 10nf decoupling capacitor between isenin+ and isenin- is preferred. the dcr sensing with thermal compensation will yield no load offset reading. resistor sensing is preferred for accurate reporting. isenin+ yes connects to the drain of high-side mosfet side of the input inductor or resistor pin. a local 0.1f ceramic capacitor is recommended. when it is not used, connect isenin+ to v in and a resistor divider with a ratio of 1/3 on isenin pins (say 499k ) in between isenin pins and then 1.5m from isenin- to ground (see figure 34 ). isenin+ is used for feedfoward compensation; tie it to input and don?t leave it open. en_pwr_cfp yes there is an internal 1s filter. decoupling capacitor is not needed, but if needed, use a low time constant one to avoid too large a shutdown delay. it will also be the output of cfp function: 34 ? strong pull-up. 25 mils spacing from other traces. rgnd yes pair up (within 20 mils) with the positive rail remote sensing line that connected to fb resistor, and routing them to the load sensing points. vsen yes used for overvoltage protection sensing and apa level sensing. caution should be taken to avoid noise coupling into this pin. fb yes pair up (within 20 mils) with the negative rail of remote sensing line that connected to rgnd, and route them to the load sensing points. reserve an rc from fb to gnd to compensate the output lagging from dac during dvid transitions. hfcomp yes connect an r to the vr output. the r value is typically equal or slightly higher (~150%) than the feedback resistor (droop resistor), fine tuned according to the high frequency transient performance. place the compensation network in close proximity to the controller.
ISL6381 49 fn8576.1 june 12, 2014 confidential submit document feedback psicomp yes the series impedance typically should be 2x-3x the impedance in type iii compensation to reduce noise coupling. place the compensation network in close proximity to the controller. comp yes place the compensation network in close proximity to the controller. typically use a 68pf or higher across fb to comp depending upon the noise coupling of the layout. dvc yes 4/3 of dac voltage. place the compensation network in close proximity to the controller. imon yes refer to gnd, not rgnd. place r and c in general proximity to the controller. the time constant of rc should be sufficient, typically <200s for vr12.5 server core and 1-2ms for desktop core applications, as an averaging function for the digital i out of vr. svdata; svclk yes very critical! greater than 13mhz signals when the svid bus is sending commands, pairing up with svalert# and routing carefully back to cpu socket. 20 mils spacing within svdata, svalert#, and svclk; and more than 30 mils to all other signals. refer to the intel individual platform design guidelines and place proper termination (pull-up) resistance for impedance matching. local decoupling capacitor is needed for the pull-up rail. these signals travel from cpu to the ISL6381 and return to cpu through ISL6381?s ground and power ground. separation between ic ground and power ground with 0 resistor is not advised. svalert# no open drain and high dv/dt pin during transitions. route it in the middle of svdata and svclk. also see above. vr_rdy no open drain and high dv/dt pin. avoid its pull-up higher than vcc. tie it to ground when not used. i2clk, i2data yes the 50khz to 1.5mhz signal when the smbus, pmbus, or i 2 c is sending commands, pairing up and routing carefully back to smbus, pmbus or i 2 c. 20 mils spacing within i2data, and i2clk; and more than 30 mils to all other signals. refer to the smbus, pmbus or i 2 c design guidelines and place proper terminated (pull-up) resistance for impedance matching. tie to vcc with 1m ? when not used. table 25. pin design and/or layout consideration (continued) pin name noise sensitive description imadr_btrm vdband_pmadr _vrsel tmx_drp_de_tc icl_spdupc_k no register setting is locked prior to soft- start. since the external resistor-divider ratio compares with th e internal resistor ratio of the vcc, their rail should be exactly tied to the same point as vcc pin, not through an rc filter. don?t use decoupling capacitors on these pins. tm_en_otp yes place ntc in close proximity to the output inductor of vr?s channel 1 and to the output rail, not close to mosfet side (see figure 24 ); the return trace should be 25 mils away from other traces. place 1k ? pull-up and decoupling capacitor (typically 0.1f) in close proximity to the controller. the pull-up resistor should be exactly tied to the same point as vcc pin, not through an rc filter. if not used, connect this pin to 1m ? /2m ? resistor divider, or tie it to vcc. vr_hot# no open drain and high dv/dt pin during transitions. avoid its pull-up rail higher than vcc. 30 mils spacing from other traces. auto_npsi yes program number of operational phases in psi1 mode and auto phase shedding threshold via a pair of paralleling resistor and capacitor from this pin to gnd. auto phase shedding is disabled when this pin tied to gnd or vcc disable. rset yes place the r in close proximity to the controller. no long pcb trace should hang on this pin or no noise node should be close to this pin. don?t use decoupling capacitor on this pin. fs_fdvid yes place the r in close proximity to the controller. no long pcb trace should hang on this pin, or no noise node should be close to this pin. don?t use decoupling capacitor on this pin. vcc yes place the decoupling capacitor in close proximity to the controller. minimize r-drop to this pin. pwm1-4 no avoid the respective pwm routing across or under other phase?s power trains/planes and current sensing network. don?t make them across or under external components of the controller. keep them at least 20 mils away from any other traces. isen[4:1]+ yes connect to the output rail side of the respective channel?s output inductor or resistor pin. decoupling is optional and might be required for long sense traces and a poor layout. table 25. pin design and/or layout consideration (continued) pin name noise sensitive description
ISL6381 50 fn8576.1 june 12, 2014 confidential submit document feedback component placement within the allotted implementation area, orient the switching components first. the switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. switching component placement should take into account power dissipation. align the output inductors and mosfets such that space between the components is minimized while creating the phase plane. place the intersil mosfet driver ic as close as possible to the mosfets they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. if possible, duplicate the same placement of these components for each phase. next, place the input and output capacitors. position the high-frequency ceramic input capacitors next to each upper mosfet drain. place the bulk input capacitors as close to the upper mosfet drains as dictat ed by the component size and dimensions. long distances between input capacitors and mosfet drains result in too much trace inductance and a reduction in capacitor performance. locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. to improve the chance of first pa ss success, it is very important to take time to follow the above outlined design guidelines and intersil generated layout check list, see more details in ? voltage regulator (vr) design materials ? on page 50 . proper planning for the layout is as important as designing the circuits. running things in a hurry, you could end up spending weeks and months to debug a poorly designed and improperly laid out board. powering up and open-loop test the ISL6381 features very easy debugging and powering up. for first-time powering up, an open-loop test can be done by applying sufficient voltage (current limi ting to 0.25a) to vcc, proper pull-up to svid bus, and signal high to tm_en_otp (>1.08v) and en_pwr_cfp (>0.9v and less than 3.3v) pins with the input voltage (vin) disconnected. 1. each pwm output should operate at maximum duty cycle and correct switching frequency. 2. the 0c-0f registers can be read via svid bus or dc-de and b0 registers via pmbus to check its proper setting. 3. if 5v drivers are used and share the same rail as vcc, the proper switching on ugates and lgates should be seen. 4. if 12v drivers are used and ca n be disconnected from vin and sourced by an external 12v supply, the proper switching on ugates and lgates should be observed. 5. if the above is not properly operating, you should check soldering joint, resistor re gister setting, power train connection or damage, i.e, shorted gates, drain and source. sometimes the gate might measure short due to residual gate charge. therefore, a measured short gate with ohmmeter cannot validate if the mosfet is damaged unless the drain to source is also measured short. 6. when rework is needed for the l/dcr matching network, use an meter across the c to see if the correct r value is measured before powering the vr up; otherwise, the current imbalance due to improper rework could damage the power trains. 7. after everything is checked, apply low input voltage (1-5v) with appropriate current limitin g (~0.5a). all phases should be switching evenly. 8. remove the pull-up from en_pwr pin, using bench power supplies, power up vcc with current limiting (typically ~ 0.25a if 5v drivers included) and slowly increase input voltage with current limiting. for typical application, vcc limited to 0.25a, vin limited to 0.5a should be safe for powering up with no load. high core-loss inductors likely need to increase the input current limiting. all phases should be switching evenly. voltage regulator (vr) design materials to support vr design and layout, intersil also developed a set of worksheets and evaluation boards, as listed in tables 26 and 25 , respectively. the tolerance band calculation (tob) worksheets for vr output regulation and imon have been developed using the root-sum-squared (rss) method wi th 3 sigma distribution point of the related components and parameters. note that the ?electrical specifications? table beginning on page 9 specifies no less than 6 sigma distribution point, not suitable for rss tob calculation. contact intersil?s local office or field support for the latest available information. isen[4:1]- yes connect to the phase node side of the respective channel?s output inductor or resistor pin with l/dcr or esl/r sen matching network in close proximity to the isen pins of vr. differentially routing back to the controller by paring with respective isen+; at least 20 mils spacing between pairs and away from other traces. each pair should not cross or go under the other channel?s switching nodes [phase, ugate, lgate] and power planes even though they are not in the same layer gnd yes this epad is the return of pwm output drivers and svid bus. use 4 or more vias to directly connect the epad to the power ground plane. avoid using only single via or 0 resistor connection to the power ground plane. general comments the layer next to the top or bottom layer is preferred to be ground layers, while the signal layers can be sandwiched in the ground layers if possible. table 25. pin design and/or layout consideration (continued) pin name noise sensitive description
ISL6381 51 fn8576.1 june 12, 2014 confidential submit document feedback table 26. available design assistance materials item description 0 vr12.5 design and validation 1 vr12.5 design worksheet for compensation and component selection 2 transient response optimization guidelines 3vout and imon tob calculator 4 svid and smbus/pmbus/i 2 c communication tool with software 5resistor register calculator 6 dynamic vid compensation calculator 7 layout design guidelines 8 tcomp and tm selection worksheet 9 fine tune ocp and droop worksheet 10 evaluation board schematics in orcad format and layout in allegro format note: for worksheets, please contac t intersil application support at www.intersil.com/design/. table 27. available evaluation boards evaluation boards pin-to-pin package socket targeted applications smbus/ pmbus/i 2 c peak efficiency iccmax (a) ISL6381eval1 isl6373 5x5 40ld ddr4 vr12/vr12.5 memory with discrete drivers and dual mosfets (configured to 2-phase for memory) yes 93%, 1.2v at 40a 60a isl6388eval1 5x5 40ld r3 vr12.5 high-end desktop and server with drmos (digital, 6-phase core) yes 94%, 1.8v at 50a 215a isl6388eval3 5x5 40ld r3 vr12.5 high-end desktop and server with discrete drivers and mosfets (digital, 6-phase core) yes 94%, 1.8v at 50a 215a isl6388eval5 5x5 40ld r3 vr12.5 server and memory with discrete drivers and dual mosfets (all digital, 6-phase core, 2x ddr3) yes 94%, 1.8v at 50a 215a 2x ddr3 yes 93%, 1.2v at 40a 60a isl6376eval1 6x6 48ld r3 vr12.5 high-end desktop and server with discrete drivers and mosfets yes 94%, 1.8v at 50a 215a isl6376eval2 6x6 48ld r3 vr12.5 high-end desktop and server with drmos yes 95%, 1.8v at 50a 215a isl6374eval1 isl6375/73 5x5 40ld h3 vr12.5 desktop/server with dual powerpak and dpak footprint no 89%, 1.8v at 40a 120a isl6373eval1 isl6374/75 5x5 40ld ddr4 vr12/vr12.5 memory with discrete drivers and dual mosfets (configured to 2-phase for memory) yes 93%, 1.2v at 40a 74a isl6373eval2 isl6374/75 5x5 40ld dd r4 vr12/vr12.5 memory with drmos (configured to 2-phase for memory) yes 93%, 1.2v at 40a 60a isl6367_67heval1 7x7 60ld r vr12/vr12.5 high-end desktop and server with discrete drivers and mosfets yes 94%, 1.8v at 50a 93%, 1.2v at 50a 220a +25a isl6367_67heval2 7x7 60ld r1 vr12/vr12.5 high-end desktop and server with drmos yes 95%, 1.8v at 50a 93%,1.2v at 50a 220a +25a isl6364aeval1 6x6 48ld h1 vr12 desktop/server (vcore or memory) no 88%, 1.2v at 50a 120a +35a isl6363eval1 7x7 60ld h1 desktop/memory no 88%, 1.2v at 50a 120a +35a isl6353eval1 5x5 40ld ddr3 memory no 94%, 1.5v at 25a 100a
ISL6381 52 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8576.1 june 12, 2014 for additional products, see www.intersil.com/en/products.html confidential submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change june 12, 2014 fn8576.1 page 4 : updated label for pin 17 from ?s m_pm_i2da? to ?sm_pm_i2data? to match the functional pin decription. page 4 : remove industrial version (irtz) page 9 : remove industrial version (irtz) for dac specs and temperature page 9 : nominal supply min value - change from 19 to 18. march 28, 2014 fn8576.0 initial release.
ISL6381 53 fn8576.1 june 12, 2014 confidential submit document feedback package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4

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